works

# Resolved:
#	si5351_driver.c

si5351_driver.c

@@ -3,8 +3,11 @@
  *
  *  Created on: 16. aug. 2024
  *      Author: Christian L. V. Madsen (OZ1CM)
- */
-#include "include/si5351_driver.h"
+ */ 
+#include "si5351_driver.h"  
+#include <stdlib.h> 
+#include <string.h>
+#include <math.h>
 
 enum{
 	SI5351_I2C_GET = 0,
@@ -12,6 +15,12 @@ enum{
 
 };
 
+static int clear_buffer(si5351_driver *inst){
+	
+	memset(inst->device_data,0, sizeof(inst->device_data));
+	
+}
+
 static int readRegister(si5351_driver *inst,uint8_t data_addr, uint8_t *data, uint32_t len){
 
 	// Write what kind of addr we would like to read from:
@@ -20,30 +29,194 @@ static int readRegister(si5351_driver *inst,uint8_t data_addr, uint8_t *data, ui
 	// Read data:
 	inst->i2c_transfer_evt(inst->i2c_transfer_inst,data,len, SI5351_I2C_GET);
 
+	//HAL_Delay(1);
 	return 0;
 }
 
-static int writeRegister(si5351_driver *inst,uint8_t data_addr, uint8_t *data, uint32_t len){
+static int writeRegister(si5351_driver *inst,uint8_t data_addr, uint32_t len){
+
+	// Set address
+	inst->device_data[0] = data_addr;
+	inst->i2c_transfer_evt(inst->i2c_transfer_inst,&inst->device_data[0],len+1, SI5351_I2C_SET);
+	clear_buffer(inst);
+	return 0;
+}
+
+static int writeRegisterbyte(si5351_driver *inst,uint8_t data_addr, uint8_t data){
+
+	// Set address
+	uint8_t buff[2] = {data_addr,data};
+	inst->i2c_transfer_evt(inst->i2c_transfer_inst,&buff[0],2, SI5351_I2C_SET);
+	clear_buffer(inst);
+	return 0;
+}
+
+int cm_setPllParamRaw(si5351_driver *inst, si5351_PLLs sel_pll, uint32_t MSNx_P1, uint32_t MSNx_P2, uint32_t MSNx_P3){
+	
+	si5351_multiSynthNxParameters_t *multiSynthNxParam = (void*)&inst->device_data[1];
+	
+				multiSynthNxParam->MSNx_P1_17_16 = (MSNx_P1 >> 16) & 0x3;
+				multiSynthNxParam->MSNx_P1_15_8 = (MSNx_P1 >> 8) & 0xff;
+				multiSynthNxParam->MSNx_P1_7_0 = MSNx_P1 & 0xff;
+
+				multiSynthNxParam->MSNx_P2_19_16 = (MSNx_P2 >> 16) & 0xf;
+				multiSynthNxParam->MSNx_P2_15_8 = (MSNx_P2 >> 8) & 0xff;
+				multiSynthNxParam->MSNx_P2_7_0 = MSNx_P2 & 0xff;
+
+				multiSynthNxParam->MSNx_P3_19_16 = (MSNx_P3 >> 16) & 0xf;
+				multiSynthNxParam->MSNx_P3_15_8 = (MSNx_P3 >> 8) & 0xff;
+				multiSynthNxParam->MSNx_P3_7_0 = MSNx_P3 & 0xff;
+	
+	switch(sel_pll){
+
+		case SI5351_PLL_A:
+			writeRegister(inst,SI5351_REG_MULTISYNTH_NA_0, sizeof(si5351_multiSynthNxParameters_t));
+		break;
+
+		case SI5351_PLL_B:
+			writeRegister(inst,SI5351_REG_MULTISYNTH_NB_0, sizeof(si5351_multiSynthNxParameters_t));
+		break;
+		
+		default:
+		break;
+	
+	}
+	
+		// reset PLL's
+	cm_resetPLLs(inst, 1,1);
+	
+	return 0;
+}
+
+int cm_setOutputMultiSynthRaw(si5351_driver *inst,si5351_Outputs clk_output, uint32_t MSx_P1, uint32_t MSx_P2, uint32_t MSx_P3){
+
+
+		si5351_multiSynthxParameters_t *multiSynthxParam = (void*)&inst->device_data[1];
+		multiSynthxParam->MSx_P1_17_16 = (MSx_P1 >> 16) & 0x3; // last division..
+		multiSynthxParam->MSx_P1_15_8 = (MSx_P1 >> 8) & 0xff;
+		multiSynthxParam->MSx_P1_7_0 = MSx_P1 & 0xff;
+
+		multiSynthxParam->MSx_P2_19_16 = (MSx_P2 >> 16) & 0xf;
+		multiSynthxParam->MSx_P2_15_8 = (MSx_P2 >> 8) & 0xff;
+		multiSynthxParam->MSx_P2_7_0 = MSx_P2 & 0xff;
+
+		multiSynthxParam->MSx_P3_19_16 = (MSx_P3 >> 16) & 0xf;
+		multiSynthxParam->MSx_P3_15_8 = (MSx_P3 >> 8) & 0xff;
+		multiSynthxParam->MSx_P3_7_0 = MSx_P3 & 0xff;
+		
+		multiSynthxParam->MSx_DIVBY4 = 0;
+		multiSynthxParam->Rx_DIV = 0;
+
+	switch(clk_output){
+
+		case SI5351_OUTPUT_0:
+			writeRegister(inst,SI5351_REG_MULTISYNTH_OUT_0, sizeof(si5351_multiSynthxParameters_t));
+		break;
+		
+		case SI5351_OUTPUT_1:
+			writeRegister(inst,SI5351_REG_MULTISYNTH_OUT_1, sizeof(si5351_multiSynthxParameters_t));
+		break;
+		
+		case SI5351_OUTPUT_2:
+			writeRegister(inst,SI5351_REG_MULTISYNTH_OUT_2, sizeof(si5351_multiSynthxParameters_t));
+		break;
+		
+		default:
+		break;
+
+
+	}
+
+	return 0;
+
+}
+
+int cm_setOutputEnable(si5351_driver *inst,si5351_Outputs clk_output, si5351_Outputs_state outputState){
+
+	si5351_outputEnableControl_t *outputEnableControl = (void*)&inst->device_data[1];
+	switch (clk_output)
+	{
+		
+		case SI5351_OUTPUT_0:
+			outputEnableControl->CLK0_OEB = outputState;
+		break; 
+		
+		case SI5351_OUTPUT_1:
+			outputEnableControl->CLK1_OEB = outputState;
+		break;
+		
+		case SI5351_OUTPUT_2:
+			outputEnableControl->CLK2_OEB = outputState;
+		break;
+		
+		default:
+		break;
+		
+	}
+		
+	writeRegister(inst,SI5351_REG_OUTPUT_ENABLE_CONTROL, sizeof(si5351_outputEnableControl_t));
+
+
+	return 0;
+}
+
+int cm_setCLKControl(si5351_driver *inst, si5351_Outputs clk_output, si5351_CLK_PDN clk_pdn){
+
+			si5351_CLK_Control_t *CLKx_control = (void*)&inst->device_data[1];
+
+			CLKx_control->CLK_PDN = clk_pdn;
+			CLKx_control->CLK_INV = 0;
+			CLKx_control->CLK_IDRV = SI5351_DRIVE_STRENGTH_8MA;
+
+	switch (clk_output)
+	{
+		
+		case SI5351_OUTPUT_0:
+			CLKx_control->CLK_SRC = 0b11;
+			CLKx_control->MSx_SRC = 0;
+			CLKx_control->MSx_INT = 0;
+			writeRegister(inst,SI5351_REG_CLK_0_CONTROL, sizeof(si5351_CLK_Control_t));
+		break;
+		
+		case SI5351_OUTPUT_1:
+			CLKx_control->CLK_SRC = 0b11;
+			CLKx_control->MSx_SRC = 1;
+			CLKx_control->MSx_INT = 0;
+			writeRegister(inst,SI5351_REG_CLK_1_CONTROL, sizeof(si5351_CLK_Control_t));
+		break;
+		
+		case SI5351_OUTPUT_2:
+			CLKx_control->CLK_SRC = 0b00;
+			CLKx_control->MSx_SRC = 0;
+			CLKx_control->MSx_INT = 1;
+			writeRegister(inst,SI5351_REG_CLK_2_CONTROL, sizeof(si5351_CLK_Control_t));
+		break;
+		
+		default:
+		break;
+		
+		
+	}
+
 
-	// Write what kind of addr we would like to read from:
-	inst->i2c_transfer_evt(inst->i2c_transfer_inst,&data_addr,1, SI5351_I2C_SET);
 
-	// Write data:
-	inst->i2c_transfer_evt(inst->i2c_transfer_inst,data,len, SI5351_I2C_SET);
 
 	return 0;
 }
 
 int cm_setInputSource(si5351_driver *inst, si5351_ClkSource clk_source){
 
+	si5351_PLLInputSource_t *pllInputSource = (void*)&inst->device_data[1];
+
 	switch(clk_source){
 
 	case SI5351_CLK_SOURCE_XTAL:
-		inst->device_data.pllInputSource.PLLA_SRC = 1;
+		pllInputSource->PLLA_SRC = 0;
+		pllInputSource->PLLB_SRC = 0;
 		break;
 
 	case SI5351_CLK_SOURCE_CLOCKSOURCE:
-		inst->device_data.pllInputSource.PLLA_SRC = 0;
+		pllInputSource->PLLA_SRC = 1;
 		break;
 
 	default:
@@ -52,17 +225,23 @@ int cm_setInputSource(si5351_driver *inst, si5351_ClkSource clk_source){
 	}
 
 	// Write to register:
-	writeRegister(inst,SI5351_REG_PLL_INPUT_SOURCE, (uint8_t*) &inst->device_data.pllInputSource, sizeof(si5351_PLLInputSource_t));
+	writeRegister(inst,SI5351_REG_PLL_INPUT_SOURCE, sizeof(si5351_PLLInputSource_t));
 
 	return 0;
 }
 
-uint8_t cm_si5351_getRevisionNumber(si5351_driver *inst){
+int cm_resetPLLs(si5351_driver *inst, uint8_t reset_PLLA, uint8_t reset_PLLB){
 
-	// Read Device Status register:
-	readRegister(inst,0x00, (uint8_t *) &inst->device_data.deviceStatus, sizeof(si5351_deviceStat_t));
+	si5351_PLL_Reset_t *PLL_Reset = (void*)&inst->device_data[1];
 
-	return inst->device_data.deviceStatus.REVID;
+	PLL_Reset->PLLA_RST = (reset_PLLA != 0)? 1 : 0;
+	PLL_Reset->PLLB_RST = (reset_PLLB != 0)? 1 : 0;
+
+	// Write to register:
+		writeRegister(inst,SI5351_REG_PLL_RESET, sizeof(si5351_PLL_Reset_t));
+
+
+		return 0;
 }
 
 int cm_si5351_init(si5351_driver *inst, void *i2c_transfer_inst, setGet_I2C_Event_fpt i2c_transfer_evt){
@@ -76,14 +255,34 @@ int cm_si5351_init(si5351_driver *inst, void *i2c_transfer_inst, setGet_I2C_Even
 
 	int ret = 0;
 
-	// SW Reset device.
-	//ret = cm_ltr390_SWreset(inst);
+	//memset(&(inst->device_data),0x00,sizeof(si5351_data));
 
-//	ret = ltr390_readAllReg(inst);
+	/* Disable all outputs setting CLKx_DIS high */
+	uint8_t temp = 0xff;
+	writeRegisterbyte(inst,SI5351_REG_OUTPUT_ENABLE_CONTROL,temp);
 
+	/* Power down all output drivers */
+	temp = 0x80;
+	writeRegisterbyte(inst,SI5351_REG_CLK_0_CONTROL,temp);
+	writeRegisterbyte(inst,SI5351_REG_CLK_1_CONTROL,temp);
+	writeRegisterbyte(inst,SI5351_REG_CLK_2_CONTROL,temp);
+	writeRegisterbyte(inst,SI5351_REG_CLK_3_CONTROL,temp);
+	writeRegisterbyte(inst,SI5351_REG_CLK_4_CONTROL,temp);
+	writeRegisterbyte(inst,SI5351_REG_CLK_5_CONTROL,temp);
+	writeRegisterbyte(inst,SI5351_REG_CLK_6_CONTROL,temp);
+	writeRegisterbyte(inst,SI5351_REG_CLK_7_CONTROL,temp);
+
+	temp = SI5351_CRYSTAL_LOAD_10PF;
+
+	writeRegisterbyte(inst,SI5351_REG_CRYSTAL_LOAD_CAPACITANCE,temp);
+	
+	// Enable xtal clk..
+	temp = 0b01000000;
+	writeRegisterbyte(inst,SI5351_REG_FANOUT_ENABLE,temp);
 	return ret;
 
 
 
 }
 
+

si5351_driver.h

@@ -52,13 +52,74 @@ typedef enum {
 	SI5351_CLK_SOURCE_XTAL = 0,
 	SI5351_CLK_SOURCE_CLOCKSOURCE = 1,
 
-
-
 }si5351_ClkSource;
 
 typedef enum {
 
+	  SI5351_CRYSTAL_LOAD_6PF = (1 << 6),
+	  SI5351_CRYSTAL_LOAD_8PF = (2 << 6),
+	  SI5351_CRYSTAL_LOAD_10PF = (3 << 6)
+
+}si5351_Xtal_Cload;
+
+typedef enum {
+
+	SI5351_PLL_A = 0,
+	SI5351_PLL_B = 1,
+
+}si5351_PLLs;
+
+typedef enum {
+
+	SI5351_OUTPUT_0 = 0,
+	SI5351_OUTPUT_1 = 1,
+	SI5351_OUTPUT_2 = 2,
+	SI5351_OUTPUT_3 = 3,
+	SI5351_OUTPUT_4 = 4,
+	SI5351_OUTPUT_5 = 5,
+	SI5351_OUTPUT_6 = 6,
+	SI5351_OUTPUT_7 = 7,
+
+}si5351_Outputs;
+
+typedef enum {
+
+	SI5351_OUTPUT_ENABLE = 0,
+	SI5351_OUTPUT_DISABLE = 1,
+
+
+}si5351_Outputs_state;
+
+typedef enum {
+	SI5351_CLK_POWER_UP = 0,
+	SI5351_CLK_POWER_DWN = 1,
+
+
+}si5351_CLK_PDN;
+
+typedef enum {
+
+	SI5351_REG_OUTPUT_ENABLE_CONTROL = 3,
 	SI5351_REG_PLL_INPUT_SOURCE = 0xf0, // Reg 15
+	SI5351_REG_CLK_0_CONTROL = 16,
+	SI5351_REG_CLK_1_CONTROL = 17,
+	SI5351_REG_CLK_2_CONTROL = 18,
+	SI5351_REG_CLK_3_CONTROL = 19,
+	SI5351_REG_CLK_4_CONTROL = 20,
+	SI5351_REG_CLK_5_CONTROL = 21,
+	SI5351_REG_CLK_6_CONTROL = 22,
+	SI5351_REG_CLK_7_CONTROL = 23,
+
+	SI5351_REG_MULTISYNTH_NA_0 = 26,
+	SI5351_REG_MULTISYNTH_NB_0 = 34,
+	SI5351_REG_MULTISYNTH_OUT_0 = 42,
+	SI5351_REG_MULTISYNTH_OUT_1 = 50,
+	SI5351_REG_MULTISYNTH_OUT_2 = 58,
+	SI5351_REG_PLL_RESET = 177,
+
+	SI5351_REG_CRYSTAL_LOAD_CAPACITANCE = 183,
+	SI5351_REG_FANOUT_ENABLE = 187,
+
 
 
 
@@ -156,16 +217,7 @@ typedef struct{
 	si5351_CLK_Disable_State CLK2_DIS_STATE : 2;
 	si5351_CLK_Disable_State CLK3_DIS_STATE : 2; // Clock x Disable State
 
-}__attribute__((packed)) si5351_CLK3_0_Control_t;
-
-typedef struct{
-
-	si5351_CLK_Disable_State CLK4_DIS_STATE : 2;
-	si5351_CLK_Disable_State CLK5_DIS_STATE : 2;
-	si5351_CLK_Disable_State CLK6_DIS_STATE : 2;
-	si5351_CLK_Disable_State CLK7_DIS_STATE : 2;
-
-}__attribute__((packed)) si5351_CLK7_4_Control_t;
+}__attribute__((packed)) si5351_CLK_Dis_Control_t;
 
 typedef struct{
 	uint8_t MSNx_P3_15_8; // register 26 & 34
@@ -198,63 +250,23 @@ typedef struct{
 }__attribute__((packed)) si5351_multiSynthxParameters_t;
 
 typedef struct {
-	uint8_t MS6_P1;
-} __attribute__((packed))si5351_multiSynth6Parameters_t;
+	uint8_t MSx_P1;
+} __attribute__((packed))si5351_multiSynth67Parameters_t;
 
 typedef struct {
-	uint8_t MS7_P1;
-} __attribute__((packed))si5351_multiSynth7Parameters_t;
-
-typedef struct{
-
-	si5351_deviceStat_t deviceStatus; // 0x00
-	si5351_interruptStatusSticky_t ISR_StatusSticky; // 0x01
-	si5351_interruptStatusMask_t ISR_StatusMask; // 0x02
-	si5351_outputEnableControl_t outputEnableControl; // 0x03
-	si5351_outputEnableControlMask_t outputEnableControlMask; // 0x09
-	si5351_PLLInputSource_t pllInputSource; // 0x0F
-
-	si5351_CLK_Control_t CLK0_control; // 0x10
-	si5351_CLK_Control_t CLK1_control; // 0x11
-	si5351_CLK_Control_t CLK2_control; // 0x12
-	si5351_CLK_Control_t CLK3_control; // 0x13
-	si5351_CLK_Control_t CLK4_control; // 0x14
-	si5351_CLK_Control_t CLK5_control; // 0x15
-	si5351_CLK_Control_t CLK6_control; // 0x16
-	si5351_CLK_Control_t CLK7_control; // 0x17
-
-	si5351_CLK3_0_Control_t clk_3_0_DisableState;
-	si5351_CLK7_4_Control_t clk_7_4_DisableState;
-
-	si5351_multiSynthNxParameters_t multiSynthNAParam;
-	si5351_multiSynthNxParameters_t multiSynthNBParam;
-
-	si5351_multiSynthxParameters_t multiSynth0Param;
-	si5351_multiSynthxParameters_t multiSynth1Param;
-	si5351_multiSynthxParameters_t multiSynth2Param;
-	si5351_multiSynthxParameters_t multiSynth3Param;
-	si5351_multiSynthxParameters_t multiSynth4Param;
-	si5351_multiSynthxParameters_t multiSynth5Param;
-
-	si5351_multiSynth6Parameters_t multiSynth6Param;
-	si5351_multiSynth7Parameters_t multiSynth7Param;
-
-	si5351_OutputDivide R6_DIV : 3;
-	uint8_t Reserved_0 : 1;
-	si5351_OutputDivide R7_DIV : 3;
+	uint8_t Reserved_0 : 5;
+	uint8_t PLLA_RST : 1;
 	uint8_t Reserved_1 : 1;
+	uint8_t PLLB_RST : 1;
 
-
-
-
-}__attribute__((packed)) si5351_data;
+} __attribute__((packed))si5351_PLL_Reset_t;
 
 typedef struct{
 
 	void *i2c_transfer_inst;
 	setGet_I2C_Event_fpt i2c_transfer_evt;
 
-	si5351_data device_data;
+	uint8_t device_data[15];
 
 
 }__attribute__((packed)) si5351_driver;
@@ -262,6 +274,14 @@ typedef struct{
 int cm_si5351_init(si5351_driver *inst, void *i2c_transfer_inst, setGet_I2C_Event_fpt i2c_transfer_evt);
 uint8_t cm_si5351_getRevisionNumber(si5351_driver *inst);
 int cm_setInputSource(si5351_driver *inst, si5351_ClkSource clk_source);
+int cm_setPLLParameters(si5351_driver *inst,si5351_PLLs sel_pll, uint32_t a, uint32_t b, uint32_t c);
+int cm_setOutputMultiSynthRaw(si5351_driver *inst,si5351_Outputs clk_output, uint32_t MSx_P1, uint32_t MSx_P2, uint32_t MSx_P3);
+int cm_setOutputEnable(si5351_driver *inst,si5351_Outputs clk_output, si5351_Outputs_state outputState);
+int cm_setCLKControl(si5351_driver *inst, si5351_Outputs clk_output, si5351_CLK_PDN clk_pdn);
+int cm_resetPLLs(si5351_driver *inst, uint8_t reset_PLLA, uint8_t reset_PLLB);
+int cm_setPllParamRaw(si5351_driver *inst, si5351_PLLs sel_pll, uint32_t MSNx_P1, uint32_t MSNx_P2, uint32_t MSNx_P3);
+
 
 
 #endif /* SI5351_DRIVER_INCLUDE_SI5351_DRIVER_H_ */
+