jgjfj

include/si5351_driver.h

@@ -11,6 +11,27 @@
 #include "stdio.h"
 #include "stdint.h"
 
+typedef enum {
+
+	SI5351_DRIVE_STRENGTH_2MA = 0,
+	SI5351_DRIVE_STRENGTH_4MA = 1,
+	SI5351_DRIVE_STRENGTH_6MA = 2,
+	SI5351_DRIVE_STRENGTH_8MA = 3,
+
+
+}si5351_DriveStrengthControl;
+
+typedef enum {
+
+	SI5351_DIS_STATE_LOW = 0,
+	SI5351_DIS_STATE_HIGH = 1,
+	SI5351_DIS_STATE_HIGH_IMPEDANCE = 2,
+	SI5351_DIS_STATE_NEVER_DISABLED = 3,
+
+
+}si5351_CLK_Disable_State;
+
+
 typedef int (*setGet_I2C_Event_fpt)(void *inst, uint8_t *data, uint32_t len, uint8_t set_get);
 
 typedef struct{
@@ -24,7 +45,7 @@ typedef struct{
 	uint8_t REVID : 2; //  Revision number of the device.
 
 
-}__attribute__((packed)) si5351_deviceStat;
+}__attribute__((packed)) si5351_deviceStat_t;
 
 typedef struct{
 
@@ -36,19 +57,99 @@ typedef struct{
 	uint8_t RESERVED : 3;
 
 
-}__attribute__((packed)) si5351_interruptStatusSticky;
+}__attribute__((packed)) si5351_interruptStatusSticky_t;
+
+typedef struct{
+
+	uint8_t CLK7_OEB : 1;
+	uint8_t CLK6_OEB : 1;
+	uint8_t CLK5_OEB : 1;
+	uint8_t CLK4_OEB : 1;
+	uint8_t CLK3_OEB : 1;
+	uint8_t CLK2_OEB : 1;
+	uint8_t CLK1_OEB : 1;
+	uint8_t CLK0_OEB : 1;
+
+
+
+}__attribute__((packed)) si5351_outputEnableControl_t;
+
+typedef struct{
+
+	uint8_t CLKIN_DIV : 2; // ClKIN Input Divider
+	uint8_t RESERVED_0 : 2;
+	uint8_t PLLB_SRC : 1; // Input Source Select for PLLB.
+	uint8_t PLLA_SRC : 1; // Input Source Select for PLLA.
+	uint8_t RESERVED_1 : 2;
+
+}__attribute__((packed)) si5351_PLLInputSource_t;
+
+typedef struct{
+
+	uint8_t CLK_PDN: 1; // ClKIN Input Divider
+	uint8_t MS0_INT : 1; // MultiSynth 0 Integer Mode
+	uint8_t MS0_SRC : 1; // MultiSynth Source Select for CLK0.
+	uint8_t CLK_INV : 1; // Input Source Select for PLLB.
+	uint8_t CLK_SRC : 2; // Input Source Select for PLLA.
+	si5351_DriveStrengthControl CLK_IDRV : 2; // CLK0 Output Rise and Fall time / Drive Strength Control
+
+}__attribute__((packed)) si5351_CLK_Control_t;
+
+typedef struct{
+
+	uint8_t CLK3_DIS_STATE: 1; // ClKIN Input Divider
+	uint8_t MS0_INT : 1; // MultiSynth 0 Integer Mode
+	uint8_t MS0_SRC : 1; // MultiSynth Source Select for CLK0.
+	uint8_t CLK_INV : 1; // Input Source Select for PLLB.
+	uint8_t CLK_SRC : 2; // Input Source Select for PLLA.
+	si5351_DriveStrengthControl CLK_IDRV : 2; // CLK0 Output Rise and Fall time / Drive Strength Control
+
+}__attribute__((packed)) si5351_CLK_Control_t;
+
+typedef struct{
+
+	si5351_CLK_Disable_State CLK3_DIS_STATE : 2;
+	si5351_CLK_Disable_State CLK2_DIS_STATE : 2;
+	si5351_CLK_Disable_State CLK1_DIS_STATE : 2;
+	si5351_CLK_Disable_State CLK0_DIS_STATE : 2;
+
+}__attribute__((packed)) si5351_CLK3_0_Control_t;
+
+typedef struct{
+
+	si5351_CLK_Disable_State CLK7_DIS_STATE : 2;
+	si5351_CLK_Disable_State CLK6_DIS_STATE : 2;
+	si5351_CLK_Disable_State CLK5_DIS_STATE : 2;
+	si5351_CLK_Disable_State CLK4_DIS_STATE : 2;
+
+}__attribute__((packed)) si5351_CLK7_4_Control_t;
 
 typedef struct{
 
 
 
-
-}__attribute__((packed)) si5351_outputEnableControl;
+}__attribute__((packed)) si5351_CLK7_4_Control_t;
 
 typedef struct{
 
-	si5351_deviceStat deviceStatus;
-	si5351_interruptStatusSticky ISR_StatusSticky;
+	si5351_deviceStat_t deviceStatus;
+	si5351_interruptStatusSticky_t ISR_StatusSticky;
+	si5351_outputEnableControl_t outputEnableControl;
+	si5351_PLLInputSource_t pllInputSource;
+
+	si5351_CLK_Control_t CLK0_control;
+	si5351_CLK_Control_t CLK1_control;
+	si5351_CLK_Control_t CLK2_control;
+	si5351_CLK_Control_t CLK3_control;
+	si5351_CLK_Control_t CLK4_control;
+	si5351_CLK_Control_t CLK5_control;
+	si5351_CLK_Control_t CLK6_control;
+	si5351_CLK_Control_t CLK7_control;
+
+	si5351_CLK3_0_Control_t clk_3_0_DisableState;
+	si5351_CLK7_4_Control_t clk_7_4_DisableState;
+
+
 
 
 }__attribute__((packed)) si5351_data;