From 2373d614c684916b250653a8c30b026a5874f788 Mon Sep 17 00:00:00 2001
From: Christian Lind Madsen <chrisser1234@live.dk>
Date: Sun, 24 Nov 2024 14:48:00 +0100
Subject: [PATCH] commit

---
 .vs/storno_cqp6xx_digital_xtal/v14/.atsuo     |  Bin 78848 -> 117248 bytes
 storno_cqp6xx_digital_xtal/Debug/cqm6xx_app.o |  Bin 12364 -> 18492 bytes
 storno_cqp6xx_digital_xtal/Debug/main.o       |  Bin 7124 -> 13076 bytes
 .../Debug/si5351_driver/si5351_driver.o       |  Bin 38348 -> 38220 bytes
 .../Debug/storno_cqp6xx_digital_xtal.elf      |  Bin 24880 -> 66160 bytes
 .../Debug/storno_cqp6xx_digital_xtal.hex      |  259 +-
 .../Debug/storno_cqp6xx_digital_xtal.lss      | 2710 +++++++++++++++--
 .../Debug/storno_cqp6xx_digital_xtal.map      |  463 +--
 .../Debug/storno_cqp6xx_digital_xtal.srec     |  259 +-
 storno_cqp6xx_digital_xtal/avr_eeprom_driver  |    2 +-
 storno_cqp6xx_digital_xtal/cqm6xx_app.c       |   31 +-
 storno_cqp6xx_digital_xtal/cqm6xx_app.h       |    2 +-
 storno_cqp6xx_digital_xtal/main.c             |   38 +-
 13 files changed, 3277 insertions(+), 487 deletions(-)

diff --git a/.vs/storno_cqp6xx_digital_xtal/v14/.atsuo b/.vs/storno_cqp6xx_digital_xtal/v14/.atsuo
index fd84d6b0bf12001c1b338cdc65c9d53624655fa1..4b8f482c8994c2ea7e0e6308ef6c3d409ea09891 100644
GIT binary patch
delta 11202
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diff --git a/storno_cqp6xx_digital_xtal/Debug/cqm6xx_app.o b/storno_cqp6xx_digital_xtal/Debug/cqm6xx_app.o
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diff --git a/storno_cqp6xx_digital_xtal/Debug/main.o b/storno_cqp6xx_digital_xtal/Debug/main.o
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diff --git a/storno_cqp6xx_digital_xtal/Debug/si5351_driver/si5351_driver.o b/storno_cqp6xx_digital_xtal/Debug/si5351_driver/si5351_driver.o
index 874de0ec8e006c4641a026f37c1108ddfad10325..3aaf2c8346ffa510d5d55fdfc80405a951678755 100644
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diff --git a/storno_cqp6xx_digital_xtal/Debug/storno_cqp6xx_digital_xtal.elf b/storno_cqp6xx_digital_xtal/Debug/storno_cqp6xx_digital_xtal.elf
index ba19f0d5361ecfec8d1b2226f1bc882c5b0eb8a0..5e2bd1b21a4e16fa4260760770781493f074b682 100644
GIT binary patch
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diff --git a/storno_cqp6xx_digital_xtal/Debug/storno_cqp6xx_digital_xtal.hex b/storno_cqp6xx_digital_xtal/Debug/storno_cqp6xx_digital_xtal.hex
index 7baffb7..9f14fd7 100644
--- a/storno_cqp6xx_digital_xtal/Debug/storno_cqp6xx_digital_xtal.hex
+++ b/storno_cqp6xx_digital_xtal/Debug/storno_cqp6xx_digital_xtal.hex
@@ -1,29 +1,240 @@
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diff --git a/storno_cqp6xx_digital_xtal/Debug/storno_cqp6xx_digital_xtal.lss b/storno_cqp6xx_digital_xtal/Debug/storno_cqp6xx_digital_xtal.lss
index eed200e..e715c85 100644
--- a/storno_cqp6xx_digital_xtal/Debug/storno_cqp6xx_digital_xtal.lss
+++ b/storno_cqp6xx_digital_xtal/Debug/storno_cqp6xx_digital_xtal.lss
@@ -3,31 +3,33 @@ storno_cqp6xx_digital_xtal.elf:     file format elf32-avr
 
 Sections:
 Idx Name          Size      VMA       LMA       File off  Algn
-  0 .data         0000001a  00803f00  0000019c  00000230  2**0
+  0 .data         00000008  00803f00  00000ec7  00000f7b  2**0
                   CONTENTS, ALLOC, LOAD, DATA
-  1 .text         0000019c  00000000  00000000  00000094  2**1
+  1 .text         00000ec2  00000000  00000000  000000b4  2**1
                   CONTENTS, ALLOC, LOAD, READONLY, CODE
-  2 .bss          0000001c  00803f1a  00803f1a  0000024a  2**0
+  2 .rodata       00000005  00008ec2  00000ec2  00000f76  2**0
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  3 .bss          00000063  00803f08  00803f08  00000f83  2**0
                   ALLOC
-  3 .comment      00000030  00000000  00000000  0000024a  2**0
+  4 .comment      00000030  00000000  00000000  00000f83  2**0
                   CONTENTS, READONLY
-  4 .note.gnu.avr.deviceinfo 0000003c  00000000  00000000  0000027c  2**2
+  5 .note.gnu.avr.deviceinfo 0000003c  00000000  00000000  00000fb4  2**2
                   CONTENTS, READONLY
-  5 .debug_aranges 000000c8  00000000  00000000  000002b8  2**3
+  6 .debug_aranges 00000260  00000000  00000000  00000ff0  2**3
                   CONTENTS, READONLY, DEBUGGING
-  6 .debug_info   00001e3d  00000000  00000000  00000380  2**0
+  7 .debug_info   0000539c  00000000  00000000  00001250  2**0
                   CONTENTS, READONLY, DEBUGGING
-  7 .debug_abbrev 00001565  00000000  00000000  000021bd  2**0
+  8 .debug_abbrev 00001d9f  00000000  00000000  000065ec  2**0
                   CONTENTS, READONLY, DEBUGGING
-  8 .debug_line   000007d0  00000000  00000000  00003722  2**0
+  9 .debug_line   000018a4  00000000  00000000  0000838b  2**0
                   CONTENTS, READONLY, DEBUGGING
-  9 .debug_frame  00000140  00000000  00000000  00003ef4  2**2
+ 10 .debug_frame  00000694  00000000  00000000  00009c30  2**2
                   CONTENTS, READONLY, DEBUGGING
- 10 .debug_str    00000e53  00000000  00000000  00004034  2**0
+ 11 .debug_str    0000227c  00000000  00000000  0000a2c4  2**0
                   CONTENTS, READONLY, DEBUGGING
- 11 .debug_loc    00000349  00000000  00000000  00004e87  2**0
+ 12 .debug_loc    000023ef  00000000  00000000  0000c540  2**0
                   CONTENTS, READONLY, DEBUGGING
- 12 .debug_ranges 00000058  00000000  00000000  000051d0  2**0
+ 13 .debug_ranges 000001a0  00000000  00000000  0000e92f  2**0
                   CONTENTS, READONLY, DEBUGGING
 
 Disassembly of section .text:
@@ -55,7 +57,7 @@ Disassembly of section .text:
   26:	21 c0       	rjmp	.+66     	; 0x6a <__bad_interrupt>
   28:	20 c0       	rjmp	.+64     	; 0x6a <__bad_interrupt>
   2a:	1f c0       	rjmp	.+62     	; 0x6a <__bad_interrupt>
-  2c:	42 c0       	rjmp	.+132    	; 0xb2 <__vector_22>
+  2c:	82 c1       	rjmp	.+772    	; 0x332 <__vector_22>
   2e:	1d c0       	rjmp	.+58     	; 0x6a <__bad_interrupt>
   30:	1c c0       	rjmp	.+56     	; 0x6a <__bad_interrupt>
   32:	1b c0       	rjmp	.+54     	; 0x6a <__bad_interrupt>
@@ -72,18 +74,18 @@ Disassembly of section .text:
   40:	1f e3       	ldi	r17, 0x3F	; 63
   42:	a0 e0       	ldi	r26, 0x00	; 0
   44:	bf e3       	ldi	r27, 0x3F	; 63
-  46:	ec e9       	ldi	r30, 0x9C	; 156
-  48:	f1 e0       	ldi	r31, 0x01	; 1
+  46:	e7 ec       	ldi	r30, 0xC7	; 199
+  48:	fe e0       	ldi	r31, 0x0E	; 14
   4a:	02 c0       	rjmp	.+4      	; 0x50 <__do_copy_data+0x10>
   4c:	05 90       	lpm	r0, Z+
   4e:	0d 92       	st	X+, r0
-  50:	aa 31       	cpi	r26, 0x1A	; 26
+  50:	a8 30       	cpi	r26, 0x08	; 8
   52:	b1 07       	cpc	r27, r17
   54:	d9 f7       	brne	.-10     	; 0x4c <__do_copy_data+0xc>
 
 00000056 <__do_clear_bss>:
   56:	2f e3       	ldi	r18, 0x3F	; 63
-  58:	aa e1       	ldi	r26, 0x1A	; 26
+  58:	a8 e0       	ldi	r26, 0x08	; 8
   5a:	bf e3       	ldi	r27, 0x3F	; 63
   5c:	01 c0       	rjmp	.+2      	; 0x60 <.do_clear_bss_start>
 
@@ -91,11 +93,11 @@ Disassembly of section .text:
   5e:	1d 92       	st	X+, r1
 
 00000060 <.do_clear_bss_start>:
-  60:	a6 33       	cpi	r26, 0x36	; 54
+  60:	ab 36       	cpi	r26, 0x6B	; 107
   62:	b2 07       	cpc	r27, r18
   64:	e1 f7       	brne	.-8      	; 0x5e <.do_clear_bss_loop>
-  66:	50 d0       	rcall	.+160    	; 0x108 <main>
-  68:	97 c0       	rjmp	.+302    	; 0x198 <_exit>
+  66:	8b d3       	rcall	.+1814   	; 0x77e <main>
+  68:	2a c7       	rjmp	.+3668   	; 0xebe <_exit>
 
 0000006a <__bad_interrupt>:
   6a:	ca cf       	rjmp	.-108    	; 0x0 <__vectors>
@@ -120,221 +122,2565 @@ void cm_EEPROM_write(uint8_t* address, uint8_t *data, uint8_t length) {
 	
 	for (uint8_t i = 0; i < length; i++) {
   7e:	c0 e0       	ldi	r28, 0x00	; 0
-  80:	07 c0       	rjmp	.+14     	; 0x90 <__EEPROM_REGION_LENGTH__+0x10>
+  80:	0a c0       	rjmp	.+20     	; 0x96 <__EEPROM_REGION_LENGTH__+0x16>
 		
-		eeprom_write_byte(address,data[i]);
-  82:	f8 01       	movw	r30, r16
-  84:	ec 0f       	add	r30, r28
-  86:	f1 1d       	adc	r31, r1
-  88:	60 81       	ld	r22, Z
-  8a:	c7 01       	movw	r24, r14
-  8c:	71 d0       	rcall	.+226    	; 0x170 <eeprom_write_byte>
+		eeprom_write_byte(address+i,data[i]);
+  82:	8c 2f       	mov	r24, r28
+  84:	90 e0       	ldi	r25, 0x00	; 0
+  86:	f8 01       	movw	r30, r16
+  88:	e8 0f       	add	r30, r24
+  8a:	f9 1f       	adc	r31, r25
+  8c:	60 81       	ld	r22, Z
+  8e:	8e 0d       	add	r24, r14
+  90:	9f 1d       	adc	r25, r15
+  92:	01 d7       	rcall	.+3586   	; 0xe96 <eeprom_write_byte>
 #include <avr/eeprom.h>
 
 void cm_EEPROM_write(uint8_t* address, uint8_t *data, uint8_t length) {
 	
 	
 	for (uint8_t i = 0; i < length; i++) {
-  8e:	cf 5f       	subi	r28, 0xFF	; 255
-  90:	cd 17       	cp	r28, r29
-  92:	b8 f3       	brcs	.-18     	; 0x82 <__EEPROM_REGION_LENGTH__+0x2>
+  94:	cf 5f       	subi	r28, 0xFF	; 255
+  96:	cd 17       	cp	r28, r29
+  98:	a0 f3       	brcs	.-24     	; 0x82 <__EEPROM_REGION_LENGTH__+0x2>
 		//NVMCTRL.CTRLA = NVMCTRL_CMD_PAGEERASEWRITE_gc;
 		
 		/* Wait until the write is complete */
 		//while (NVMCTRL.STATUS & NVMCTRL_EEBUSY_bm);
 	}
 }
-  94:	df 91       	pop	r29
-  96:	cf 91       	pop	r28
-  98:	1f 91       	pop	r17
-  9a:	0f 91       	pop	r16
-  9c:	ff 90       	pop	r15
-  9e:	ef 90       	pop	r14
-  a0:	08 95       	ret
+  9a:	df 91       	pop	r29
+  9c:	cf 91       	pop	r28
+  9e:	1f 91       	pop	r17
+  a0:	0f 91       	pop	r16
+  a2:	ff 90       	pop	r15
+  a4:	ef 90       	pop	r14
+  a6:	08 95       	ret
 
-000000a2 <cm_EEPROM_read>:
+000000a8 <cm_EEPROM_read>:
 
 
 void cm_EEPROM_read(uint8_t* address, uint8_t *data, uint8_t length) {
-  a2:	cf 93       	push	r28
-  a4:	df 93       	push	r29
-  a6:	eb 01       	movw	r28, r22
+  a8:	cf 92       	push	r12
+  aa:	df 92       	push	r13
+  ac:	ef 92       	push	r14
+  ae:	ff 92       	push	r15
+  b0:	0f 93       	push	r16
+  b2:	1f 93       	push	r17
+  b4:	cf 93       	push	r28
+  b6:	df 93       	push	r29
+  b8:	6c 01       	movw	r12, r24
+  ba:	7b 01       	movw	r14, r22
+  bc:	d4 2f       	mov	r29, r20
 	
-	data[0] = eeprom_read_byte(address);
-  a8:	5b d0       	rcall	.+182    	; 0x160 <eeprom_read_byte>
-  aa:	88 83       	st	Y, r24
+	for (uint8_t i = 0; i < length; i++) {
+  be:	c0 e0       	ldi	r28, 0x00	; 0
+  c0:	0b c0       	rjmp	.+22     	; 0xd8 <cm_EEPROM_read+0x30>
+		data[i] = eeprom_read_byte(address+i);
+  c2:	8c 2f       	mov	r24, r28
+  c4:	90 e0       	ldi	r25, 0x00	; 0
+  c6:	87 01       	movw	r16, r14
+  c8:	08 0f       	add	r16, r24
+  ca:	19 1f       	adc	r17, r25
+  cc:	8c 0d       	add	r24, r12
+  ce:	9d 1d       	adc	r25, r13
+  d0:	da d6       	rcall	.+3508   	; 0xe86 <eeprom_read_byte>
+  d2:	f8 01       	movw	r30, r16
+  d4:	80 83       	st	Z, r24
+}
+
+
+void cm_EEPROM_read(uint8_t* address, uint8_t *data, uint8_t length) {
+	
+	for (uint8_t i = 0; i < length; i++) {
+  d6:	cf 5f       	subi	r28, 0xFF	; 255
+  d8:	cd 17       	cp	r28, r29
+  da:	98 f3       	brcs	.-26     	; 0xc2 <cm_EEPROM_read+0x1a>
 
 		// Directly read the data from NVMCTRL.DATA 
 		data[i] = NVMCTRL.DATA;
 		
 	}*/
 }
-  ac:	df 91       	pop	r29
-  ae:	cf 91       	pop	r28
-  b0:	08 95       	ret
+  dc:	df 91       	pop	r29
+  de:	cf 91       	pop	r28
+  e0:	1f 91       	pop	r17
+  e2:	0f 91       	pop	r16
+  e4:	ff 90       	pop	r15
+  e6:	ef 90       	pop	r14
+  e8:	df 90       	pop	r13
+  ea:	cf 90       	pop	r12
+  ec:	08 95       	ret
 
-000000b2 <__vector_22>:
+000000ee <gpio_get_level>:
+		return 0;
+}
+
+int gpio_get_level(avr_gpio_ports port, uint8_t pin){
+			
+			switch (port)
+  ee:	81 11       	cpse	r24, r1
+  f0:	0d c0       	rjmp	.+26     	; 0x10c <__DATA_REGION_LENGTH__+0xc>
+			{
+				
+				case GPIO_PORTA:
+				return (PORTA.IN & (1 << pin)) ? 1 : 0;
+  f2:	20 91 08 04 	lds	r18, 0x0408	; 0x800408 <startCode+0x7f7546>
+  f6:	30 e0       	ldi	r19, 0x00	; 0
+  f8:	02 c0       	rjmp	.+4      	; 0xfe <gpio_get_level+0x10>
+  fa:	35 95       	asr	r19
+  fc:	27 95       	ror	r18
+  fe:	6a 95       	dec	r22
+ 100:	e2 f7       	brpl	.-8      	; 0xfa <gpio_get_level+0xc>
+ 102:	81 e0       	ldi	r24, 0x01	; 1
+ 104:	20 ff       	sbrs	r18, 0
+ 106:	80 e0       	ldi	r24, 0x00	; 0
+ 108:	90 e0       	ldi	r25, 0x00	; 0
+ 10a:	08 95       	ret
+				break;
+				
+				default:
+				break;
+			}
+	return 0;
+ 10c:	80 e0       	ldi	r24, 0x00	; 0
+ 10e:	90 e0       	ldi	r25, 0x00	; 0
+}
+ 110:	08 95       	ret
+
+00000112 <i2c_reset>:
+	*data = TWI0.MDATA;
+	
+	// Send stop condition
+	TWI0.MCTRLB = TWI_MCMD_STOP_gc;
+	return 0;  // Success
+}
+ 112:	e0 e1       	ldi	r30, 0x10	; 16
+ 114:	f8 e0       	ldi	r31, 0x08	; 8
+ 116:	84 81       	ldd	r24, Z+4	; 0x04
+ 118:	88 60       	ori	r24, 0x08	; 8
+ 11a:	84 83       	std	Z+4, r24	; 0x04
+ 11c:	81 e0       	ldi	r24, 0x01	; 1
+ 11e:	85 83       	std	Z+5, r24	; 0x05
+ 120:	08 95       	ret
+
+00000122 <i2c_write_devAddr>:
+ 122:	80 93 17 08 	sts	0x0817, r24	; 0x800817 <startCode+0x7f7955>
+ 126:	80 91 15 08 	lds	r24, 0x0815	; 0x800815 <startCode+0x7f7953>
+ 12a:	80 7c       	andi	r24, 0xC0	; 192
+ 12c:	e1 f3       	breq	.-8      	; 0x126 <i2c_write_devAddr+0x4>
+ 12e:	90 91 15 08 	lds	r25, 0x0815	; 0x800815 <startCode+0x7f7953>
+ 132:	89 2f       	mov	r24, r25
+ 134:	80 71       	andi	r24, 0x10	; 16
+ 136:	94 ff       	sbrs	r25, 4
+ 138:	04 c0       	rjmp	.+8      	; 0x142 <i2c_write_devAddr+0x20>
+ 13a:	83 e0       	ldi	r24, 0x03	; 3
+ 13c:	80 93 14 08 	sts	0x0814, r24	; 0x800814 <startCode+0x7f7952>
+ 140:	81 e0       	ldi	r24, 0x01	; 1
+ 142:	08 95       	ret
+
+00000144 <i2c_write>:
+
+int i2c_write(uint8_t dev_addr, void *data, uint32_t len){
+ 144:	cf 92       	push	r12
+ 146:	df 92       	push	r13
+ 148:	ef 92       	push	r14
+ 14a:	ff 92       	push	r15
+ 14c:	cf 93       	push	r28
+ 14e:	df 93       	push	r29
+ 150:	eb 01       	movw	r28, r22
+ 152:	69 01       	movw	r12, r18
+ 154:	7a 01       	movw	r14, r20
+	
+	// Check length
+	if(len == 0) return CM_I2C_NOK;
+ 156:	23 2b       	or	r18, r19
+ 158:	24 2b       	or	r18, r20
+ 15a:	25 2b       	or	r18, r21
+ 15c:	81 f1       	breq	.+96     	; 0x1be <i2c_write+0x7a>
+	
+	// Make a pointer to data
+	uint8_t *dp = data;
+	
+	// Send register address to I2C device, we would like to read from..
+	if(i2c_write_devAddr(dev_addr) != CM_I2C_OK)return CM_I2C_NOK;
+ 15e:	e1 df       	rcall	.-62     	; 0x122 <i2c_write_devAddr>
+ 160:	81 11       	cpse	r24, r1
+ 162:	30 c0       	rjmp	.+96     	; 0x1c4 <i2c_write+0x80>
+	
+	do
+	{
+		// Prepare and send new data.
+		TWI0.MDATA = *dp++;
+ 164:	9e 01       	movw	r18, r28
+ 166:	2f 5f       	subi	r18, 0xFF	; 255
+ 168:	3f 4f       	sbci	r19, 0xFF	; 255
+ 16a:	88 81       	ld	r24, Y
+ 16c:	80 93 18 08 	sts	0x0818, r24	; 0x800818 <startCode+0x7f7956>
+		
+		while (!(TWI0.MSTATUS & TWI_WIF_bm));
+ 170:	80 91 15 08 	lds	r24, 0x0815	; 0x800815 <startCode+0x7f7953>
+ 174:	86 ff       	sbrs	r24, 6
+ 176:	fc cf       	rjmp	.-8      	; 0x170 <i2c_write+0x2c>
+	
+		if (TWI0.MSTATUS & TWI_RXACK_bm) {
+ 178:	80 91 15 08 	lds	r24, 0x0815	; 0x800815 <startCode+0x7f7953>
+ 17c:	84 ff       	sbrs	r24, 4
+ 17e:	06 c0       	rjmp	.+12     	; 0x18c <i2c_write+0x48>
+			// NACK received
+			TWI0.MCTRLB = TWI_MCMD_STOP_gc;  // Send stop condition
+ 180:	83 e0       	ldi	r24, 0x03	; 3
+ 182:	80 93 14 08 	sts	0x0814, r24	; 0x800814 <startCode+0x7f7952>
+			return 1;  // Error: NACK received
+ 186:	81 e0       	ldi	r24, 0x01	; 1
+ 188:	90 e0       	ldi	r25, 0x00	; 0
+ 18a:	1e c0       	rjmp	.+60     	; 0x1c8 <i2c_write+0x84>
+		}
+		
+		// Check for bus error and reset if it happens..
+		if (TWI0.MSTATUS & (TWI_ARBLOST_bm | TWI_BUSERR_bm)) {
+ 18c:	80 91 15 08 	lds	r24, 0x0815	; 0x800815 <startCode+0x7f7953>
+ 190:	8c 70       	andi	r24, 0x0C	; 12
+ 192:	21 f0       	breq	.+8      	; 0x19c <i2c_write+0x58>
+            i2c_reset();
+ 194:	be df       	rcall	.-132    	; 0x112 <i2c_reset>
+            return 1;
+ 196:	81 e0       	ldi	r24, 0x01	; 1
+ 198:	90 e0       	ldi	r25, 0x00	; 0
+ 19a:	16 c0       	rjmp	.+44     	; 0x1c8 <i2c_write+0x84>
+        }
+
+        if (TWI0.MSTATUS & TWI_RXACK_bm)
+ 19c:	80 91 15 08 	lds	r24, 0x0815	; 0x800815 <startCode+0x7f7953>
+ 1a0:	84 fd       	sbrc	r24, 4
+ 1a2:	07 c0       	rjmp	.+14     	; 0x1b2 <i2c_write+0x6e>
+            break;
+			
+	}while(--len);
+ 1a4:	81 e0       	ldi	r24, 0x01	; 1
+ 1a6:	c8 1a       	sub	r12, r24
+ 1a8:	d1 08       	sbc	r13, r1
+ 1aa:	e1 08       	sbc	r14, r1
+ 1ac:	f1 08       	sbc	r15, r1
+	if(i2c_write_devAddr(dev_addr) != CM_I2C_OK)return CM_I2C_NOK;
+	
+	do
+	{
+		// Prepare and send new data.
+		TWI0.MDATA = *dp++;
+ 1ae:	e9 01       	movw	r28, r18
+        }
+
+        if (TWI0.MSTATUS & TWI_RXACK_bm)
+            break;
+			
+	}while(--len);
+ 1b0:	c9 f6       	brne	.-78     	; 0x164 <i2c_write+0x20>
+	
+	// Send stop condition
+	TWI0.MCTRLB = TWI_MCMD_STOP_gc;
+ 1b2:	83 e0       	ldi	r24, 0x03	; 3
+ 1b4:	80 93 14 08 	sts	0x0814, r24	; 0x800814 <startCode+0x7f7952>
+	
+	
+	return CM_I2C_OK;
+ 1b8:	80 e0       	ldi	r24, 0x00	; 0
+ 1ba:	90 e0       	ldi	r25, 0x00	; 0
+ 1bc:	05 c0       	rjmp	.+10     	; 0x1c8 <i2c_write+0x84>
+}
+
+int i2c_write(uint8_t dev_addr, void *data, uint32_t len){
+	
+	// Check length
+	if(len == 0) return CM_I2C_NOK;
+ 1be:	8f ef       	ldi	r24, 0xFF	; 255
+ 1c0:	9f ef       	ldi	r25, 0xFF	; 255
+ 1c2:	02 c0       	rjmp	.+4      	; 0x1c8 <i2c_write+0x84>
+	
+	// Make a pointer to data
+	uint8_t *dp = data;
+	
+	// Send register address to I2C device, we would like to read from..
+	if(i2c_write_devAddr(dev_addr) != CM_I2C_OK)return CM_I2C_NOK;
+ 1c4:	8f ef       	ldi	r24, 0xFF	; 255
+ 1c6:	9f ef       	ldi	r25, 0xFF	; 255
+	// Send stop condition
+	TWI0.MCTRLB = TWI_MCMD_STOP_gc;
+	
+	
+	return CM_I2C_OK;
+}
+ 1c8:	df 91       	pop	r29
+ 1ca:	cf 91       	pop	r28
+ 1cc:	ff 90       	pop	r15
+ 1ce:	ef 90       	pop	r14
+ 1d0:	df 90       	pop	r13
+ 1d2:	cf 90       	pop	r12
+ 1d4:	08 95       	ret
+
+000001d6 <i2c_read>:
+
+int i2c_read(uint8_t dev_addr, void *data, uint32_t len){
+ 1d6:	cf 92       	push	r12
+ 1d8:	df 92       	push	r13
+ 1da:	ef 92       	push	r14
+ 1dc:	ff 92       	push	r15
+ 1de:	cf 93       	push	r28
+ 1e0:	df 93       	push	r29
+ 1e2:	eb 01       	movw	r28, r22
+ 1e4:	69 01       	movw	r12, r18
+ 1e6:	7a 01       	movw	r14, r20
+	
+	    uint8_t *dp = data;
+
+	    if (len == 0)
+ 1e8:	23 2b       	or	r18, r19
+ 1ea:	24 2b       	or	r18, r20
+ 1ec:	25 2b       	or	r18, r21
+ 1ee:	69 f1       	breq	.+90     	; 0x24a <i2c_read+0x74>
+	    return 1;
+
+		// Send register address to I2C device, we would like to read from..
+		if(i2c_write_devAddr(dev_addr | 1) != CM_I2C_OK)return CM_I2C_NOK;
+ 1f0:	81 60       	ori	r24, 0x01	; 1
+ 1f2:	97 df       	rcall	.-210    	; 0x122 <i2c_write_devAddr>
+ 1f4:	88 23       	and	r24, r24
+ 1f6:	c9 f0       	breq	.+50     	; 0x22a <i2c_read+0x54>
+ 1f8:	2b c0       	rjmp	.+86     	; 0x250 <i2c_read+0x7a>
+
+    while (len--) {
+		
+	    while (!(TWI0.MSTATUS & (TWI_WIF_bm | TWI_RIF_bm)));
+ 1fa:	80 91 15 08 	lds	r24, 0x0815	; 0x800815 <startCode+0x7f7953>
+ 1fe:	80 7c       	andi	r24, 0xC0	; 192
+ 200:	e1 f3       	breq	.-8      	; 0x1fa <i2c_read+0x24>
+		
+	    *dp++ = TWI0.MDATA;
+ 202:	ce 01       	movw	r24, r28
+ 204:	01 96       	adiw	r24, 0x01	; 1
+ 206:	20 91 18 08 	lds	r18, 0x0818	; 0x800818 <startCode+0x7f7956>
+ 20a:	28 83       	st	Y, r18
+	    if (len == 0) {
+ 20c:	41 15       	cp	r20, r1
+ 20e:	51 05       	cpc	r21, r1
+ 210:	61 05       	cpc	r22, r1
+ 212:	71 05       	cpc	r23, r1
+ 214:	21 f4       	brne	.+8      	; 0x21e <i2c_read+0x48>
+		    TWI0.MCTRLB = TWI_ACKACT_NACK_gc;
+ 216:	24 e0       	ldi	r18, 0x04	; 4
+ 218:	20 93 14 08 	sts	0x0814, r18	; 0x800814 <startCode+0x7f7952>
+ 21c:	03 c0       	rjmp	.+6      	; 0x224 <i2c_read+0x4e>
+		    } else {
+		    TWI0.MCTRLB = TWI_ACKACT_ACK_gc | TWI_MCMD_RECVTRANS_gc;
+ 21e:	22 e0       	ldi	r18, 0x02	; 2
+ 220:	20 93 14 08 	sts	0x0814, r18	; 0x800814 <startCode+0x7f7952>
+ 224:	6a 01       	movw	r12, r20
+ 226:	7b 01       	movw	r14, r22
+	
+	
+	return CM_I2C_OK;
+}
+
+int i2c_read(uint8_t dev_addr, void *data, uint32_t len){
+ 228:	ec 01       	movw	r28, r24
+	    return 1;
+
+		// Send register address to I2C device, we would like to read from..
+		if(i2c_write_devAddr(dev_addr | 1) != CM_I2C_OK)return CM_I2C_NOK;
+
+    while (len--) {
+ 22a:	b7 01       	movw	r22, r14
+ 22c:	a6 01       	movw	r20, r12
+ 22e:	41 50       	subi	r20, 0x01	; 1
+ 230:	51 09       	sbc	r21, r1
+ 232:	61 09       	sbc	r22, r1
+ 234:	71 09       	sbc	r23, r1
+ 236:	cd 28       	or	r12, r13
+ 238:	ce 28       	or	r12, r14
+ 23a:	cf 28       	or	r12, r15
+ 23c:	f1 f6       	brne	.-68     	; 0x1fa <i2c_read+0x24>
+		    TWI0.MCTRLB = TWI_ACKACT_ACK_gc | TWI_MCMD_RECVTRANS_gc;
+	    }
+    }
+	
+		// Send stop condition
+	TWI0.MCTRLB = TWI_MCMD_STOP_gc;
+ 23e:	83 e0       	ldi	r24, 0x03	; 3
+ 240:	80 93 14 08 	sts	0x0814, r24	; 0x800814 <startCode+0x7f7952>
+
+	    return 0;
+ 244:	80 e0       	ldi	r24, 0x00	; 0
+ 246:	90 e0       	ldi	r25, 0x00	; 0
+ 248:	05 c0       	rjmp	.+10     	; 0x254 <i2c_read+0x7e>
+int i2c_read(uint8_t dev_addr, void *data, uint32_t len){
+	
+	    uint8_t *dp = data;
+
+	    if (len == 0)
+	    return 1;
+ 24a:	81 e0       	ldi	r24, 0x01	; 1
+ 24c:	90 e0       	ldi	r25, 0x00	; 0
+ 24e:	02 c0       	rjmp	.+4      	; 0x254 <i2c_read+0x7e>
+
+		// Send register address to I2C device, we would like to read from..
+		if(i2c_write_devAddr(dev_addr | 1) != CM_I2C_OK)return CM_I2C_NOK;
+ 250:	8f ef       	ldi	r24, 0xFF	; 255
+ 252:	9f ef       	ldi	r25, 0xFF	; 255
+	TWI0.MCTRLB = TWI_MCMD_STOP_gc;
+
+	    return 0;
+	
+	
+}
+ 254:	df 91       	pop	r29
+ 256:	cf 91       	pop	r28
+ 258:	ff 90       	pop	r15
+ 25a:	ef 90       	pop	r14
+ 25c:	df 90       	pop	r13
+ 25e:	cf 90       	pop	r12
+ 260:	08 95       	ret
+
+00000262 <i2c_IsDeviceReady>:
+
+int i2c_IsDeviceReady(uint8_t dev_addr){
+	
+	TWI0.MADDR = dev_addr | 0;
+ 262:	80 93 17 08 	sts	0x0817, r24	; 0x800817 <startCode+0x7f7955>
+	
+	// Wait for acknowledgment
+	while (!(TWI0.MSTATUS & TWI_WIF_bm));
+ 266:	80 91 15 08 	lds	r24, 0x0815	; 0x800815 <startCode+0x7f7953>
+ 26a:	86 ff       	sbrs	r24, 6
+ 26c:	fc cf       	rjmp	.-8      	; 0x266 <i2c_IsDeviceReady+0x4>
+	
+	if (TWI0.MSTATUS & TWI_RXACK_bm) {
+ 26e:	80 91 15 08 	lds	r24, 0x0815	; 0x800815 <startCode+0x7f7953>
+ 272:	84 ff       	sbrs	r24, 4
+ 274:	06 c0       	rjmp	.+12     	; 0x282 <i2c_IsDeviceReady+0x20>
+		// NACK received
+		TWI0.MCTRLB = TWI_MCMD_STOP_gc;  // Send stop condition
+ 276:	83 e0       	ldi	r24, 0x03	; 3
+ 278:	80 93 14 08 	sts	0x0814, r24	; 0x800814 <startCode+0x7f7952>
+		return 1;  // Error: NACK received
+ 27c:	81 e0       	ldi	r24, 0x01	; 1
+ 27e:	90 e0       	ldi	r25, 0x00	; 0
+ 280:	08 95       	ret
+	}
+	
+	// Send stop condition
+	TWI0.MCTRLB = TWI_MCMD_STOP_gc;
+ 282:	83 e0       	ldi	r24, 0x03	; 3
+ 284:	80 93 14 08 	sts	0x0814, r24	; 0x800814 <startCode+0x7f7952>
+	return CM_I2C_OK;  // Success
+ 288:	80 e0       	ldi	r24, 0x00	; 0
+ 28a:	90 e0       	ldi	r25, 0x00	; 0
+	
+}
+ 28c:	08 95       	ret
+
+0000028e <cm_i2c_init>:
+
+
+int cm_i2c_init(void *i2c_inst){
+	
+	PORTA.DIR &= ~(1 << 2);  // Clear bit 2 (PA2)
+ 28e:	e0 e0       	ldi	r30, 0x00	; 0
+ 290:	f4 e0       	ldi	r31, 0x04	; 4
+ 292:	80 81       	ld	r24, Z
+ 294:	8b 7f       	andi	r24, 0xFB	; 251
+ 296:	80 83       	st	Z, r24
+	PORTA.DIR &= ~(1 << 3);  // Clear bit 3 (PA3)
+ 298:	80 81       	ld	r24, Z
+ 29a:	87 7f       	andi	r24, 0xF7	; 247
+ 29c:	80 83       	st	Z, r24
+
+	// Set the baud rate for 100kHz with a typical rise time of 300 ns
+	TWI0.MBAUD = 11;
+ 29e:	a0 e1       	ldi	r26, 0x10	; 16
+ 2a0:	b8 e0       	ldi	r27, 0x08	; 8
+ 2a2:	8b e0       	ldi	r24, 0x0B	; 11
+ 2a4:	16 96       	adiw	r26, 0x06	; 6
+ 2a6:	8c 93       	st	X, r24
+ 2a8:	16 97       	sbiw	r26, 0x06	; 6
+
+	// Enable the TWI master and set it to enable operation
+	TWI0.MCTRLA = TWI_ENABLE_bm;
+ 2aa:	81 e0       	ldi	r24, 0x01	; 1
+ 2ac:	13 96       	adiw	r26, 0x03	; 3
+ 2ae:	8c 93       	st	X, r24
+ 2b0:	13 97       	sbiw	r26, 0x03	; 3
+		
+	/* Set bus state idle */
+	TWI0.MSTATUS = TWI_BUSSTATE_IDLE_gc;
+ 2b2:	15 96       	adiw	r26, 0x05	; 5
+ 2b4:	8c 93       	st	X, r24
+		
+	// Enable the internal pull-ups for PA2 (SDA) and PA3 (SCL)
+	PORTA.PIN2CTRL = PORT_PULLUPEN_bm;
+ 2b6:	88 e0       	ldi	r24, 0x08	; 8
+ 2b8:	82 8b       	std	Z+18, r24	; 0x12
+	PORTA.PIN3CTRL = PORT_PULLUPEN_bm;
+ 2ba:	83 8b       	std	Z+19, r24	; 0x13
+	return CM_I2C_OK;
+}
+ 2bc:	80 e0       	ldi	r24, 0x00	; 0
+ 2be:	90 e0       	ldi	r25, 0x00	; 0
+ 2c0:	08 95       	ret
+
+000002c2 <cm_i2c_addDev>:
+
+
+
+int cm_i2c_addDev(cm_i2c_device_t *inst, void *i2c_inst, uint8_t dev_addr){
+ 2c2:	ef 92       	push	r14
+ 2c4:	ff 92       	push	r15
+ 2c6:	0f 93       	push	r16
+ 2c8:	1f 93       	push	r17
+ 2ca:	cf 93       	push	r28
+ 2cc:	8c 01       	movw	r16, r24
+ 2ce:	7b 01       	movw	r14, r22
+ 2d0:	c4 2f       	mov	r28, r20
+
+	//if(i2c_inst == NULL) return CM_I2C_NOK;
+
+	// Check if device responds!
+	if(i2c_IsDeviceReady((dev_addr << 1)) != CM_I2C_OK)return CM_I2C_NO_DEVICE;
+ 2d2:	84 2f       	mov	r24, r20
+ 2d4:	88 0f       	add	r24, r24
+ 2d6:	c5 df       	rcall	.-118    	; 0x262 <i2c_IsDeviceReady>
+ 2d8:	00 97       	sbiw	r24, 0x00	; 0
+ 2da:	49 f4       	brne	.+18     	; 0x2ee <cm_i2c_addDev+0x2c>
+	
+	// add device info if device responds!
+	inst->i2c_transfer_inst = i2c_inst;
+ 2dc:	f8 01       	movw	r30, r16
+ 2de:	e0 82       	st	Z, r14
+ 2e0:	f1 82       	std	Z+1, r15	; 0x01
+	inst->dev_addr = (dev_addr << 1) & 0b11111110;
+ 2e2:	4c 2f       	mov	r20, r28
+ 2e4:	50 e0       	ldi	r21, 0x00	; 0
+ 2e6:	44 0f       	add	r20, r20
+ 2e8:	55 1f       	adc	r21, r21
+ 2ea:	42 83       	std	Z+2, r20	; 0x02
+
+	return CM_I2C_OK;
+ 2ec:	02 c0       	rjmp	.+4      	; 0x2f2 <cm_i2c_addDev+0x30>
+int cm_i2c_addDev(cm_i2c_device_t *inst, void *i2c_inst, uint8_t dev_addr){
+
+	//if(i2c_inst == NULL) return CM_I2C_NOK;
+
+	// Check if device responds!
+	if(i2c_IsDeviceReady((dev_addr << 1)) != CM_I2C_OK)return CM_I2C_NO_DEVICE;
+ 2ee:	8e ef       	ldi	r24, 0xFE	; 254
+ 2f0:	9f ef       	ldi	r25, 0xFF	; 255
+	// add device info if device responds!
+	inst->i2c_transfer_inst = i2c_inst;
+	inst->dev_addr = (dev_addr << 1) & 0b11111110;
+
+	return CM_I2C_OK;
+}
+ 2f2:	cf 91       	pop	r28
+ 2f4:	1f 91       	pop	r17
+ 2f6:	0f 91       	pop	r16
+ 2f8:	ff 90       	pop	r15
+ 2fa:	ef 90       	pop	r14
+ 2fc:	08 95       	ret
+
+000002fe <cm_i2c_transfer>:
+
+
+int cm_i2c_transfer(cm_i2c_device_t *inst, uint8_t *data, uint32_t len, i2c_setget_cm_t set_get){
+ 2fe:	0f 93       	push	r16
+
+	if(inst == NULL) return CM_I2C_NOK;
+ 300:	00 97       	sbiw	r24, 0x00	; 0
+ 302:	81 f0       	breq	.+32     	; 0x324 <cm_i2c_transfer+0x26>
+ 304:	fc 01       	movw	r30, r24
+
+	// Check if device responds!
+	//if(i2c_IsDeviceReady(inst->dev_addr) != CM_I2C_OK)return CM_I2C_NO_DEVICE;
+
+	switch(set_get){
+ 306:	00 23       	and	r16, r16
+ 308:	19 f0       	breq	.+6      	; 0x310 <cm_i2c_transfer+0x12>
+ 30a:	01 30       	cpi	r16, 0x01	; 1
+ 30c:	31 f0       	breq	.+12     	; 0x31a <cm_i2c_transfer+0x1c>
+ 30e:	0d c0       	rjmp	.+26     	; 0x32a <cm_i2c_transfer+0x2c>
+
+		case I2C_CM_GET:
+		//HAL_I2C_Master_Receive(inst->i2c_transfer_inst, inst->dev_addr, data, len, 1);
+		i2c_read(inst->dev_addr, data, len);
+ 310:	82 81       	ldd	r24, Z+2	; 0x02
+ 312:	61 df       	rcall	.-318    	; 0x1d6 <i2c_read>
+		break;
+
+
+	}
+
+	return CM_I2C_OK;
+ 314:	80 e0       	ldi	r24, 0x00	; 0
+ 316:	90 e0       	ldi	r25, 0x00	; 0
+	switch(set_get){
+
+		case I2C_CM_GET:
+		//HAL_I2C_Master_Receive(inst->i2c_transfer_inst, inst->dev_addr, data, len, 1);
+		i2c_read(inst->dev_addr, data, len);
+		break;
+ 318:	0a c0       	rjmp	.+20     	; 0x32e <cm_i2c_transfer+0x30>
+
+		case I2C_CM_SET:
+		//HAL_I2C_Master_Transmit(inst->i2c_transfer_inst, inst->dev_addr, data, len, 1);
+		i2c_write(inst->dev_addr, data, len);
+ 31a:	82 81       	ldd	r24, Z+2	; 0x02
+ 31c:	13 df       	rcall	.-474    	; 0x144 <i2c_write>
+		break;
+
+
+	}
+
+	return CM_I2C_OK;
+ 31e:	80 e0       	ldi	r24, 0x00	; 0
+ 320:	90 e0       	ldi	r25, 0x00	; 0
+		break;
+
+		case I2C_CM_SET:
+		//HAL_I2C_Master_Transmit(inst->i2c_transfer_inst, inst->dev_addr, data, len, 1);
+		i2c_write(inst->dev_addr, data, len);
+		break;
+ 322:	05 c0       	rjmp	.+10     	; 0x32e <cm_i2c_transfer+0x30>
+}
+
+
+int cm_i2c_transfer(cm_i2c_device_t *inst, uint8_t *data, uint32_t len, i2c_setget_cm_t set_get){
+
+	if(inst == NULL) return CM_I2C_NOK;
+ 324:	8f ef       	ldi	r24, 0xFF	; 255
+ 326:	9f ef       	ldi	r25, 0xFF	; 255
+ 328:	02 c0       	rjmp	.+4      	; 0x32e <cm_i2c_transfer+0x30>
+		break;
+
+
+	}
+
+	return CM_I2C_OK;
+ 32a:	80 e0       	ldi	r24, 0x00	; 0
+ 32c:	90 e0       	ldi	r25, 0x00	; 0
+
+}
+ 32e:	0f 91       	pop	r16
+ 330:	08 95       	ret
+
+00000332 <__vector_22>:
 #define BAUD_RATE 9600
 
 static void *s_inst = NULL;
  get_UART_Event_fpt uart_rx_evt_fpt = NULL;
 
 ISR(USART0_RXC_vect) {
-  b2:	1f 92       	push	r1
-  b4:	0f 92       	push	r0
-  b6:	0f b6       	in	r0, 0x3f	; 63
-  b8:	0f 92       	push	r0
-  ba:	11 24       	eor	r1, r1
-  bc:	2f 93       	push	r18
-  be:	3f 93       	push	r19
-  c0:	4f 93       	push	r20
-  c2:	5f 93       	push	r21
-  c4:	6f 93       	push	r22
-  c6:	7f 93       	push	r23
-  c8:	8f 93       	push	r24
-  ca:	9f 93       	push	r25
-  cc:	af 93       	push	r26
-  ce:	bf 93       	push	r27
-  d0:	ef 93       	push	r30
-  d2:	ff 93       	push	r31
+ 332:	1f 92       	push	r1
+ 334:	0f 92       	push	r0
+ 336:	0f b6       	in	r0, 0x3f	; 63
+ 338:	0f 92       	push	r0
+ 33a:	11 24       	eor	r1, r1
+ 33c:	2f 93       	push	r18
+ 33e:	3f 93       	push	r19
+ 340:	4f 93       	push	r20
+ 342:	5f 93       	push	r21
+ 344:	6f 93       	push	r22
+ 346:	7f 93       	push	r23
+ 348:	8f 93       	push	r24
+ 34a:	9f 93       	push	r25
+ 34c:	af 93       	push	r26
+ 34e:	bf 93       	push	r27
+ 350:	ef 93       	push	r30
+ 352:	ff 93       	push	r31
 	// Read received data
 	if(uart_rx_evt_fpt != NULL) uart_rx_evt_fpt(USART0.RXDATAL);
-  d4:	e0 91 1a 3f 	lds	r30, 0x3F1A	; 0x803f1a <__data_end>
-  d8:	f0 91 1b 3f 	lds	r31, 0x3F1B	; 0x803f1b <__data_end+0x1>
-  dc:	30 97       	sbiw	r30, 0x00	; 0
-  de:	19 f0       	breq	.+6      	; 0xe6 <__vector_22+0x34>
-  e0:	80 91 00 08 	lds	r24, 0x0800	; 0x800800 <__RODATA_PM_OFFSET__+0x7f8800>
-  e4:	09 95       	icall
+ 354:	e0 91 08 3f 	lds	r30, 0x3F08	; 0x803f08 <__data_end>
+ 358:	f0 91 09 3f 	lds	r31, 0x3F09	; 0x803f09 <__data_end+0x1>
+ 35c:	30 97       	sbiw	r30, 0x00	; 0
+ 35e:	19 f0       	breq	.+6      	; 0x366 <__vector_22+0x34>
+ 360:	80 91 00 08 	lds	r24, 0x0800	; 0x800800 <startCode+0x7f793e>
+ 364:	09 95       	icall
 	//cm_uart_send(USART0.RXDATAL);
 	
 }
-  e6:	ff 91       	pop	r31
-  e8:	ef 91       	pop	r30
-  ea:	bf 91       	pop	r27
-  ec:	af 91       	pop	r26
-  ee:	9f 91       	pop	r25
-  f0:	8f 91       	pop	r24
-  f2:	7f 91       	pop	r23
-  f4:	6f 91       	pop	r22
-  f6:	5f 91       	pop	r21
-  f8:	4f 91       	pop	r20
-  fa:	3f 91       	pop	r19
-  fc:	2f 91       	pop	r18
-  fe:	0f 90       	pop	r0
- 100:	0f be       	out	0x3f, r0	; 63
- 102:	0f 90       	pop	r0
- 104:	1f 90       	pop	r1
- 106:	18 95       	reti
+ 366:	ff 91       	pop	r31
+ 368:	ef 91       	pop	r30
+ 36a:	bf 91       	pop	r27
+ 36c:	af 91       	pop	r26
+ 36e:	9f 91       	pop	r25
+ 370:	8f 91       	pop	r24
+ 372:	7f 91       	pop	r23
+ 374:	6f 91       	pop	r22
+ 376:	5f 91       	pop	r21
+ 378:	4f 91       	pop	r20
+ 37a:	3f 91       	pop	r19
+ 37c:	2f 91       	pop	r18
+ 37e:	0f 90       	pop	r0
+ 380:	0f be       	out	0x3f, r0	; 63
+ 382:	0f 90       	pop	r0
+ 384:	1f 90       	pop	r1
+ 386:	18 95       	reti
 
-00000108 <main>:
-		
-int main(void)
-{
+00000388 <cm_uart_init>:
+
+
+void cm_uart_init(void *rtx_inst, get_UART_Event_fpt uart_rx_evt_fp){
+ 388:	cf 93       	push	r28
+ 38a:	df 93       	push	r29
+ 38c:	1f 92       	push	r1
+ 38e:	cd b7       	in	r28, 0x3d	; 61
+ 390:	de b7       	in	r29, 0x3e	; 62
+ 392:	ac 01       	movw	r20, r24
 	
+		//For interrupt-driven USART operation, global interrupts must be disabled during the initialization
+		cli();
+ 394:	f8 94       	cli
+		
+	    // Calculate and set baud rate register (3.33 MHz / (16 * 9600) - 1)
+	    uint16_t baud = 1388;//(F_CPU / (16 * BAUD_RATE)) - 1;
+	    USART0.BAUD = baud;
+ 396:	e0 e0       	ldi	r30, 0x00	; 0
+ 398:	f8 e0       	ldi	r31, 0x08	; 8
+ 39a:	2c e6       	ldi	r18, 0x6C	; 108
+ 39c:	35 e0       	ldi	r19, 0x05	; 5
+ 39e:	20 87       	std	Z+8, r18	; 0x08
+ 3a0:	31 87       	std	Z+9, r19	; 0x09
 
-	cm_EEPROM_read(0x00,data,1);
- 108:	41 e0       	ldi	r20, 0x01	; 1
- 10a:	6d e1       	ldi	r22, 0x1D	; 29
- 10c:	7f e3       	ldi	r23, 0x3F	; 63
- 10e:	80 e0       	ldi	r24, 0x00	; 0
- 110:	90 e0       	ldi	r25, 0x00	; 0
- 112:	c7 df       	rcall	.-114    	; 0xa2 <cm_EEPROM_read>
+	    // Configure USART0 for 8-bit data, no parity, 1 stop bit
+	    USART0.CTRLC = USART_CMODE_ASYNCHRONOUS_gc |  // Asynchronous mode
+ 3a2:	93 e0       	ldi	r25, 0x03	; 3
+ 3a4:	97 83       	std	Z+7, r25	; 0x07
+	    USART_CHSIZE_8BIT_gc |        // 8-bit character size
+	    USART_PMODE_DISABLED_gc;      // No parity
+
+	    // Enable receiver, transmitter, and receive complete interrupt
+	    USART0.CTRLB = USART_RXEN_bm |  // Enable receiver
+ 3a6:	90 ec       	ldi	r25, 0xC0	; 192
+ 3a8:	96 83       	std	Z+6, r25	; 0x06
+	    USART_TXEN_bm; // Enable transmitter
+	    
+		if((uart_rx_evt_fp != NULL) || (rtx_inst != NULL)){
+ 3aa:	61 15       	cp	r22, r1
+ 3ac:	71 05       	cpc	r23, r1
+ 3ae:	11 f4       	brne	.+4      	; 0x3b4 <cm_uart_init+0x2c>
+ 3b0:	45 2b       	or	r20, r21
+ 3b2:	39 f0       	breq	.+14     	; 0x3c2 <cm_uart_init+0x3a>
+			// Enable RX interrupt
+			USART0.CTRLA = USART_RXCIE_bm;  // Enable receive interrupt
+ 3b4:	80 e8       	ldi	r24, 0x80	; 128
+ 3b6:	80 93 05 08 	sts	0x0805, r24	; 0x800805 <startCode+0x7f7943>
+			
+			s_inst = rtx_inst;
+			uart_rx_evt_fpt = uart_rx_evt_fp;
+ 3ba:	60 93 08 3f 	sts	0x3F08, r22	; 0x803f08 <__data_end>
+ 3be:	70 93 09 3f 	sts	0x3F09, r23	; 0x803f09 <__data_end+0x1>
+		}
+
+		
+		// Clear any existing receive complete interrupt flag by reading RXDATAL
+		if (USART0.STATUS & USART_RXCIF_bm) {
+ 3c2:	80 91 04 08 	lds	r24, 0x0804	; 0x800804 <startCode+0x7f7942>
+ 3c6:	88 23       	and	r24, r24
+ 3c8:	24 f4       	brge	.+8      	; 0x3d2 <cm_uart_init+0x4a>
+			volatile uint8_t dummy = USART0.RXDATAL;  // Read RXDATAL to clear the flag
+ 3ca:	80 91 00 08 	lds	r24, 0x0800	; 0x800800 <startCode+0x7f793e>
+ 3ce:	89 83       	std	Y+1, r24	; 0x01
+			(void)dummy;  // Silence unused variable warning
+ 3d0:	89 81       	ldd	r24, Y+1	; 0x01
+		}
+		
+		PORTA.DIRSET = (1 << 6);  // Set PA1 (TX) as output
+ 3d2:	e0 e0       	ldi	r30, 0x00	; 0
+ 3d4:	f4 e0       	ldi	r31, 0x04	; 4
+ 3d6:	80 e4       	ldi	r24, 0x40	; 64
+ 3d8:	81 83       	std	Z+1, r24	; 0x01
+		PORTA.DIRCLR = (1 << 7);  // Set PA2 (RX) as input
+ 3da:	80 e8       	ldi	r24, 0x80	; 128
+ 3dc:	82 83       	std	Z+2, r24	; 0x02
+	    // Enable global interrupts
+	    sei();
+ 3de:	78 94       	sei
+
+	
+}
+ 3e0:	0f 90       	pop	r0
+ 3e2:	df 91       	pop	r29
+ 3e4:	cf 91       	pop	r28
+ 3e6:	08 95       	ret
+
+000003e8 <cm_msgSync_Byte_DecodeSC>:
+
+int cm_msgSync_Byte_DecodeSC(uint8_t rx_byte){
+	
+	static cm_msg_startcode_states_t state = CM_MSGSYNC_STATE_INIT;
+	
+	switch (state)
+ 3e8:	e0 91 43 3f 	lds	r30, 0x3F43	; 0x803f43 <state.1832>
+ 3ec:	e2 30       	cpi	r30, 0x02	; 2
+ 3ee:	29 f1       	breq	.+74     	; 0x43a <__LOCK_REGION_LENGTH__+0x3a>
+ 3f0:	28 f4       	brcc	.+10     	; 0x3fc <cm_msgSync_Byte_DecodeSC+0x14>
+ 3f2:	ee 23       	and	r30, r30
+ 3f4:	41 f0       	breq	.+16     	; 0x406 <__LOCK_REGION_LENGTH__+0x6>
+ 3f6:	e1 30       	cpi	r30, 0x01	; 1
+ 3f8:	91 f0       	breq	.+36     	; 0x41e <__LOCK_REGION_LENGTH__+0x1e>
+ 3fa:	40 c0       	rjmp	.+128    	; 0x47c <__LOCK_REGION_LENGTH__+0x7c>
+ 3fc:	e3 30       	cpi	r30, 0x03	; 3
+ 3fe:	59 f1       	breq	.+86     	; 0x456 <__LOCK_REGION_LENGTH__+0x56>
+ 400:	e4 30       	cpi	r30, 0x04	; 4
+ 402:	b9 f1       	breq	.+110    	; 0x472 <__LOCK_REGION_LENGTH__+0x72>
+ 404:	3b c0       	rjmp	.+118    	; 0x47c <__LOCK_REGION_LENGTH__+0x7c>
+	{
+		case CM_MSGSYNC_STATE_INIT:
+			state = (rx_byte == startCode[state])? CM_MSGSYNC_STATE_2 : CM_MSGSYNC_STATE_INIT;
+ 406:	f0 e0       	ldi	r31, 0x00	; 0
+ 408:	ee 53       	subi	r30, 0x3E	; 62
+ 40a:	f1 47       	sbci	r31, 0x71	; 113
+ 40c:	20 81       	ld	r18, Z
+ 40e:	91 e0       	ldi	r25, 0x01	; 1
+ 410:	28 13       	cpse	r18, r24
+ 412:	90 e0       	ldi	r25, 0x00	; 0
+ 414:	90 93 43 3f 	sts	0x3F43, r25	; 0x803f43 <state.1832>
+		default:
+			state = CM_MSGSYNC_STATE_INIT;
+		break;
+	}
+	
+	return 1;
+ 418:	81 e0       	ldi	r24, 0x01	; 1
+ 41a:	90 e0       	ldi	r25, 0x00	; 0
+	
+	switch (state)
+	{
+		case CM_MSGSYNC_STATE_INIT:
+			state = (rx_byte == startCode[state])? CM_MSGSYNC_STATE_2 : CM_MSGSYNC_STATE_INIT;
+		break;
+ 41c:	08 95       	ret
+		
+		case CM_MSGSYNC_STATE_2:
+			state = (rx_byte == startCode[state])? CM_MSGSYNC_STATE_3 : CM_MSGSYNC_STATE_INIT;
+ 41e:	f0 e0       	ldi	r31, 0x00	; 0
+ 420:	ee 53       	subi	r30, 0x3E	; 62
+ 422:	f1 47       	sbci	r31, 0x71	; 113
+ 424:	90 81       	ld	r25, Z
+ 426:	89 13       	cpse	r24, r25
+ 428:	02 c0       	rjmp	.+4      	; 0x42e <__LOCK_REGION_LENGTH__+0x2e>
+ 42a:	82 e0       	ldi	r24, 0x02	; 2
+ 42c:	01 c0       	rjmp	.+2      	; 0x430 <__LOCK_REGION_LENGTH__+0x30>
+ 42e:	80 e0       	ldi	r24, 0x00	; 0
+ 430:	80 93 43 3f 	sts	0x3F43, r24	; 0x803f43 <state.1832>
+		default:
+			state = CM_MSGSYNC_STATE_INIT;
+		break;
+	}
+	
+	return 1;
+ 434:	81 e0       	ldi	r24, 0x01	; 1
+ 436:	90 e0       	ldi	r25, 0x00	; 0
+			state = (rx_byte == startCode[state])? CM_MSGSYNC_STATE_2 : CM_MSGSYNC_STATE_INIT;
+		break;
+		
+		case CM_MSGSYNC_STATE_2:
+			state = (rx_byte == startCode[state])? CM_MSGSYNC_STATE_3 : CM_MSGSYNC_STATE_INIT;
+		break;
+ 438:	08 95       	ret
+		
+		case CM_MSGSYNC_STATE_3:
+			state = (rx_byte == startCode[state])? CM_MSGSYNC_STATE_4 : CM_MSGSYNC_STATE_INIT;
+ 43a:	f0 e0       	ldi	r31, 0x00	; 0
+ 43c:	ee 53       	subi	r30, 0x3E	; 62
+ 43e:	f1 47       	sbci	r31, 0x71	; 113
+ 440:	90 81       	ld	r25, Z
+ 442:	89 13       	cpse	r24, r25
+ 444:	02 c0       	rjmp	.+4      	; 0x44a <__LOCK_REGION_LENGTH__+0x4a>
+ 446:	83 e0       	ldi	r24, 0x03	; 3
+ 448:	01 c0       	rjmp	.+2      	; 0x44c <__LOCK_REGION_LENGTH__+0x4c>
+ 44a:	80 e0       	ldi	r24, 0x00	; 0
+ 44c:	80 93 43 3f 	sts	0x3F43, r24	; 0x803f43 <state.1832>
+		default:
+			state = CM_MSGSYNC_STATE_INIT;
+		break;
+	}
+	
+	return 1;
+ 450:	81 e0       	ldi	r24, 0x01	; 1
+ 452:	90 e0       	ldi	r25, 0x00	; 0
+			state = (rx_byte == startCode[state])? CM_MSGSYNC_STATE_3 : CM_MSGSYNC_STATE_INIT;
+		break;
+		
+		case CM_MSGSYNC_STATE_3:
+			state = (rx_byte == startCode[state])? CM_MSGSYNC_STATE_4 : CM_MSGSYNC_STATE_INIT;
+		break;
+ 454:	08 95       	ret
+		
+		case CM_MSGSYNC_STATE_4:
+			state = (rx_byte == startCode[state])? CM_MSGSYNC_STATE_5 : CM_MSGSYNC_STATE_INIT;
+ 456:	f0 e0       	ldi	r31, 0x00	; 0
+ 458:	ee 53       	subi	r30, 0x3E	; 62
+ 45a:	f1 47       	sbci	r31, 0x71	; 113
+ 45c:	90 81       	ld	r25, Z
+ 45e:	89 13       	cpse	r24, r25
+ 460:	02 c0       	rjmp	.+4      	; 0x466 <__LOCK_REGION_LENGTH__+0x66>
+ 462:	84 e0       	ldi	r24, 0x04	; 4
+ 464:	01 c0       	rjmp	.+2      	; 0x468 <__LOCK_REGION_LENGTH__+0x68>
+ 466:	80 e0       	ldi	r24, 0x00	; 0
+ 468:	80 93 43 3f 	sts	0x3F43, r24	; 0x803f43 <state.1832>
+		default:
+			state = CM_MSGSYNC_STATE_INIT;
+		break;
+	}
+	
+	return 1;
+ 46c:	81 e0       	ldi	r24, 0x01	; 1
+ 46e:	90 e0       	ldi	r25, 0x00	; 0
+			state = (rx_byte == startCode[state])? CM_MSGSYNC_STATE_4 : CM_MSGSYNC_STATE_INIT;
+		break;
+		
+		case CM_MSGSYNC_STATE_4:
+			state = (rx_byte == startCode[state])? CM_MSGSYNC_STATE_5 : CM_MSGSYNC_STATE_INIT;
+		break;
+ 470:	08 95       	ret
+		
+		case CM_MSGSYNC_STATE_5:
+			state = CM_MSGSYNC_STATE_INIT;
+ 472:	10 92 43 3f 	sts	0x3F43, r1	; 0x803f43 <state.1832>
+			return 0;
+ 476:	80 e0       	ldi	r24, 0x00	; 0
+ 478:	90 e0       	ldi	r25, 0x00	; 0
+ 47a:	08 95       	ret
+		break;
+		
+		default:
+			state = CM_MSGSYNC_STATE_INIT;
+ 47c:	10 92 43 3f 	sts	0x3F43, r1	; 0x803f43 <state.1832>
+		break;
+	}
+	
+	return 1;
+ 480:	81 e0       	ldi	r24, 0x01	; 1
+ 482:	90 e0       	ldi	r25, 0x00	; 0
+	
+	
+}
+ 484:	08 95       	ret
+
+00000486 <cm_msg_DecodeMsg_Byte>:
+	
+	static cm_msg_decode_states_t state = CM_MSG_WAIT_FOR_STARTCODE;
+	static cm_data_msg_t msg;
+	static uint8_t data_bytes_idx = 0;
+	
+	switch (state)
+ 486:	90 91 42 3f 	lds	r25, 0x3F42	; 0x803f42 <state.1843>
+ 48a:	93 30       	cpi	r25, 0x03	; 3
+ 48c:	d1 f0       	breq	.+52     	; 0x4c2 <cm_msg_DecodeMsg_Byte+0x3c>
+ 48e:	28 f4       	brcc	.+10     	; 0x49a <cm_msg_DecodeMsg_Byte+0x14>
+ 490:	99 23       	and	r25, r25
+ 492:	41 f0       	breq	.+16     	; 0x4a4 <cm_msg_DecodeMsg_Byte+0x1e>
+ 494:	91 30       	cpi	r25, 0x01	; 1
+ 496:	79 f0       	breq	.+30     	; 0x4b6 <cm_msg_DecodeMsg_Byte+0x30>
+ 498:	47 c0       	rjmp	.+142    	; 0x528 <cm_msg_DecodeMsg_Byte+0xa2>
+ 49a:	94 30       	cpi	r25, 0x04	; 4
+ 49c:	d1 f0       	breq	.+52     	; 0x4d2 <cm_msg_DecodeMsg_Byte+0x4c>
+ 49e:	95 30       	cpi	r25, 0x05	; 5
+ 4a0:	29 f1       	breq	.+74     	; 0x4ec <cm_msg_DecodeMsg_Byte+0x66>
+ 4a2:	42 c0       	rjmp	.+132    	; 0x528 <cm_msg_DecodeMsg_Byte+0xa2>
+	{
+		case CM_MSG_WAIT_FOR_STARTCODE:
+			if(!cm_msgSync_Byte_DecodeSC(rx_byte)) state = CM_MSG_DECODE_STATE_GET_SIZE_BYTE;
+ 4a4:	a1 df       	rcall	.-190    	; 0x3e8 <cm_msgSync_Byte_DecodeSC>
+ 4a6:	89 2b       	or	r24, r25
+ 4a8:	19 f4       	brne	.+6      	; 0x4b0 <cm_msg_DecodeMsg_Byte+0x2a>
+ 4aa:	81 e0       	ldi	r24, 0x01	; 1
+ 4ac:	80 93 42 3f 	sts	0x3F42, r24	; 0x803f42 <state.1843>
+			data_bytes_idx = 0;
+ 4b0:	10 92 41 3f 	sts	0x3F41, r1	; 0x803f41 <data_bytes_idx.1845>
+		break;
+ 4b4:	39 c0       	rjmp	.+114    	; 0x528 <cm_msg_DecodeMsg_Byte+0xa2>
+		
+		case CM_MSG_DECODE_STATE_GET_SIZE_BYTE:
+			msg.msg_data_size = rx_byte;
+ 4b6:	80 93 0a 3f 	sts	0x3F0A, r24	; 0x803f0a <msg.1844>
+			state = CM_MSG_DECODE_STATE_GET_CRC_BYTE1;
+ 4ba:	83 e0       	ldi	r24, 0x03	; 3
+ 4bc:	80 93 42 3f 	sts	0x3F42, r24	; 0x803f42 <state.1843>
+			
+		break;
+ 4c0:	33 c0       	rjmp	.+102    	; 0x528 <cm_msg_DecodeMsg_Byte+0xa2>
+		
+		case CM_MSG_DECODE_STATE_GET_CRC_BYTE1:
+			msg.msg_data_crc = (rx_byte << 8) & 0xff00;
+ 4c2:	ea e0       	ldi	r30, 0x0A	; 10
+ 4c4:	ff e3       	ldi	r31, 0x3F	; 63
+ 4c6:	11 82       	std	Z+1, r1	; 0x01
+ 4c8:	82 83       	std	Z+2, r24	; 0x02
+			state = CM_MSG_DECODE_STATE_GET_CRC_BYTE2;
+ 4ca:	84 e0       	ldi	r24, 0x04	; 4
+ 4cc:	80 93 42 3f 	sts	0x3F42, r24	; 0x803f42 <state.1843>
+		break;
+ 4d0:	2b c0       	rjmp	.+86     	; 0x528 <cm_msg_DecodeMsg_Byte+0xa2>
+		
+		case CM_MSG_DECODE_STATE_GET_CRC_BYTE2:
+			msg.msg_data_crc |= rx_byte & 0xff;
+ 4d2:	ea e0       	ldi	r30, 0x0A	; 10
+ 4d4:	ff e3       	ldi	r31, 0x3F	; 63
+ 4d6:	21 81       	ldd	r18, Z+1	; 0x01
+ 4d8:	32 81       	ldd	r19, Z+2	; 0x02
+ 4da:	a9 01       	movw	r20, r18
+ 4dc:	48 2b       	or	r20, r24
+ 4de:	ca 01       	movw	r24, r20
+ 4e0:	81 83       	std	Z+1, r24	; 0x01
+ 4e2:	92 83       	std	Z+2, r25	; 0x02
+			state = CM_MSG_DECODE_STATE_GET_DATA;
+ 4e4:	85 e0       	ldi	r24, 0x05	; 5
+ 4e6:	80 93 42 3f 	sts	0x3F42, r24	; 0x803f42 <state.1843>
+		break;
+ 4ea:	1e c0       	rjmp	.+60     	; 0x528 <cm_msg_DecodeMsg_Byte+0xa2>
+			
+		case CM_MSG_DECODE_STATE_GET_DATA:
+			msg.msg_data[data_bytes_idx] = rx_byte;
+ 4ec:	90 91 41 3f 	lds	r25, 0x3F41	; 0x803f41 <data_bytes_idx.1845>
+ 4f0:	e9 2f       	mov	r30, r25
+ 4f2:	f0 e0       	ldi	r31, 0x00	; 0
+ 4f4:	e6 5f       	subi	r30, 0xF6	; 246
+ 4f6:	f0 4c       	sbci	r31, 0xC0	; 192
+ 4f8:	83 83       	std	Z+3, r24	; 0x03
+			data_bytes_idx++;
+ 4fa:	81 e0       	ldi	r24, 0x01	; 1
+ 4fc:	89 0f       	add	r24, r25
+ 4fe:	80 93 41 3f 	sts	0x3F41, r24	; 0x803f41 <data_bytes_idx.1845>
+			if(data_bytes_idx >= msg.msg_data_size){
+ 502:	90 91 0a 3f 	lds	r25, 0x3F0A	; 0x803f0a <msg.1844>
+ 506:	89 17       	cp	r24, r25
+ 508:	78 f0       	brcs	.+30     	; 0x528 <cm_msg_DecodeMsg_Byte+0xa2>
+				// calculate CRC..
+				
+				// Run function pointer msg evt..
+				s_msg_cmplete_evt_fpt(s_msg_cmplete_evt_inst,&(msg.msg_data[0]));
+ 50a:	e0 91 46 3f 	lds	r30, 0x3F46	; 0x803f46 <s_msg_cmplete_evt_fpt>
+ 50e:	f0 91 47 3f 	lds	r31, 0x3F47	; 0x803f47 <s_msg_cmplete_evt_fpt+0x1>
+ 512:	6d e0       	ldi	r22, 0x0D	; 13
+ 514:	7f e3       	ldi	r23, 0x3F	; 63
+ 516:	80 91 44 3f 	lds	r24, 0x3F44	; 0x803f44 <s_msg_cmplete_evt_inst>
+ 51a:	90 91 45 3f 	lds	r25, 0x3F45	; 0x803f45 <s_msg_cmplete_evt_inst+0x1>
+ 51e:	09 95       	icall
+				state = CM_MSG_WAIT_FOR_STARTCODE;
+ 520:	10 92 42 3f 	sts	0x3F42, r1	; 0x803f42 <state.1843>
+				data_bytes_idx = 0;
+ 524:	10 92 41 3f 	sts	0x3F41, r1	; 0x803f41 <data_bytes_idx.1845>
+				
+			}
+		break;
+	}
+	return 0;
+}
+ 528:	80 e0       	ldi	r24, 0x00	; 0
+ 52a:	90 e0       	ldi	r25, 0x00	; 0
+ 52c:	08 95       	ret
+
+0000052e <cm_MsgCompleteEvt_Register>:
+
+void cm_MsgCompleteEvt_Register(void *msg_cmplete_evt_inst, Get_msgComplete_Event_fpt msg_cmplete_evt_fp){
+	
+	if((msg_cmplete_evt_inst == NULL) || (msg_cmplete_evt_fp == NULL))return;
+ 52e:	00 97       	sbiw	r24, 0x00	; 0
+ 530:	59 f0       	breq	.+22     	; 0x548 <cm_MsgCompleteEvt_Register+0x1a>
+ 532:	61 15       	cp	r22, r1
+ 534:	71 05       	cpc	r23, r1
+ 536:	41 f0       	breq	.+16     	; 0x548 <cm_MsgCompleteEvt_Register+0x1a>
+	
+	s_msg_cmplete_evt_inst = msg_cmplete_evt_inst;
+ 538:	80 93 44 3f 	sts	0x3F44, r24	; 0x803f44 <s_msg_cmplete_evt_inst>
+ 53c:	90 93 45 3f 	sts	0x3F45, r25	; 0x803f45 <s_msg_cmplete_evt_inst+0x1>
+	s_msg_cmplete_evt_fpt = msg_cmplete_evt_fp;
+ 540:	60 93 46 3f 	sts	0x3F46, r22	; 0x803f46 <s_msg_cmplete_evt_fpt>
+ 544:	70 93 47 3f 	sts	0x3F47, r23	; 0x803f47 <s_msg_cmplete_evt_fpt+0x1>
+ 548:	08 95       	ret
+
+0000054a <isStructValid>:
+	storno_pll_param_msg temp_msg;
+	uint8_t *msg_ptr = (void*)&temp_msg;
+
+static uint8_t isStructValid(storno_xtal_app_t *inst){
+	
+		if(inst->si5351_dev == NULL) return 1;
+ 54a:	fc 01       	movw	r30, r24
+ 54c:	22 81       	ldd	r18, Z+2	; 0x02
+ 54e:	33 81       	ldd	r19, Z+3	; 0x03
+ 550:	23 2b       	or	r18, r19
+ 552:	21 f0       	breq	.+8      	; 0x55c <isStructValid+0x12>
+		if(inst == NULL)return 1;
+ 554:	89 2b       	or	r24, r25
+ 556:	21 f4       	brne	.+8      	; 0x560 <isStructValid+0x16>
+ 558:	81 e0       	ldi	r24, 0x01	; 1
+ 55a:	08 95       	ret
+	storno_pll_param_msg temp_msg;
+	uint8_t *msg_ptr = (void*)&temp_msg;
+
+static uint8_t isStructValid(storno_xtal_app_t *inst){
+	
+		if(inst->si5351_dev == NULL) return 1;
+ 55c:	81 e0       	ldi	r24, 0x01	; 1
+ 55e:	08 95       	ret
+		if(inst == NULL)return 1;
+		
+		return 0;
+ 560:	80 e0       	ldi	r24, 0x00	; 0
+} 
+ 562:	08 95       	ret
+
+00000564 <cqm_setPLLParam>:
+	}
+	
+	
+}
+
+static void cqm_setPLLParam(storno_xtal_app_t *inst, si5351_PLLs pll_num, si5351_Outputs output){
+ 564:	9f 92       	push	r9
+ 566:	af 92       	push	r10
+ 568:	bf 92       	push	r11
+ 56a:	cf 92       	push	r12
+ 56c:	df 92       	push	r13
+ 56e:	ef 92       	push	r14
+ 570:	ff 92       	push	r15
+ 572:	0f 93       	push	r16
+ 574:	1f 93       	push	r17
+ 576:	cf 93       	push	r28
+ 578:	df 93       	push	r29
+ 57a:	ec 01       	movw	r28, r24
+ 57c:	94 2e       	mov	r9, r20
+	
+	cm_setPllParamRaw(inst->si5351_dev,pll_num, inst->pll_param_ptr->MSNx_P1, inst->pll_param_ptr->MSNx_P2, inst->pll_param_ptr->MSNx_P3);
+ 57e:	ec 81       	ldd	r30, Y+4	; 0x04
+ 580:	fd 81       	ldd	r31, Y+5	; 0x05
+ 582:	a1 84       	ldd	r10, Z+9	; 0x09
+ 584:	b2 84       	ldd	r11, Z+10	; 0x0a
+ 586:	c3 84       	ldd	r12, Z+11	; 0x0b
+ 588:	d4 84       	ldd	r13, Z+12	; 0x0c
+ 58a:	e5 80       	ldd	r14, Z+5	; 0x05
+ 58c:	f6 80       	ldd	r15, Z+6	; 0x06
+ 58e:	07 81       	ldd	r16, Z+7	; 0x07
+ 590:	10 85       	ldd	r17, Z+8	; 0x08
+ 592:	21 81       	ldd	r18, Z+1	; 0x01
+ 594:	32 81       	ldd	r19, Z+2	; 0x02
+ 596:	43 81       	ldd	r20, Z+3	; 0x03
+ 598:	54 81       	ldd	r21, Z+4	; 0x04
+ 59a:	8a 81       	ldd	r24, Y+2	; 0x02
+ 59c:	9b 81       	ldd	r25, Y+3	; 0x03
+ 59e:	4a d2       	rcall	.+1172   	; 0xa34 <cm_setPllParamRaw>
 	#else
 		//round up by default
 		__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
 	#endif
 
 	__builtin_avr_delay_cycles(__ticks_dc);
- 114:	2a e6       	ldi	r18, 0x6A	; 106
- 116:	84 e0       	ldi	r24, 0x04	; 4
- 118:	91 e0       	ldi	r25, 0x01	; 1
- 11a:	21 50       	subi	r18, 0x01	; 1
- 11c:	80 40       	sbci	r24, 0x00	; 0
- 11e:	90 40       	sbci	r25, 0x00	; 0
- 120:	e1 f7       	brne	.-8      	; 0x11a <main+0x12>
- 122:	00 c0       	rjmp	.+0      	; 0x124 <main+0x1c>
+ 5a0:	81 e4       	ldi	r24, 0x41	; 65
+ 5a2:	93 e0       	ldi	r25, 0x03	; 3
+ 5a4:	01 97       	sbiw	r24, 0x01	; 1
+ 5a6:	f1 f7       	brne	.-4      	; 0x5a4 <cqm_setPLLParam+0x40>
+ 5a8:	00 00       	nop
+	_delay_ms(1);
+	cm_setOutputMultiSynthRaw(inst->si5351_dev,output, inst->pll_param_ptr->MSx_P1, inst->pll_param_ptr->MSx_P2, inst->pll_param_ptr->MSx_P3);
+ 5aa:	ec 81       	ldd	r30, Y+4	; 0x04
+ 5ac:	fd 81       	ldd	r31, Y+5	; 0x05
+ 5ae:	a5 88       	ldd	r10, Z+21	; 0x15
+ 5b0:	b6 88       	ldd	r11, Z+22	; 0x16
+ 5b2:	c7 88       	ldd	r12, Z+23	; 0x17
+ 5b4:	d0 8c       	ldd	r13, Z+24	; 0x18
+ 5b6:	e1 88       	ldd	r14, Z+17	; 0x11
+ 5b8:	f2 88       	ldd	r15, Z+18	; 0x12
+ 5ba:	03 89       	ldd	r16, Z+19	; 0x13
+ 5bc:	14 89       	ldd	r17, Z+20	; 0x14
+ 5be:	25 85       	ldd	r18, Z+13	; 0x0d
+ 5c0:	36 85       	ldd	r19, Z+14	; 0x0e
+ 5c2:	47 85       	ldd	r20, Z+15	; 0x0f
+ 5c4:	50 89       	ldd	r21, Z+16	; 0x10
+ 5c6:	69 2d       	mov	r22, r9
+ 5c8:	8a 81       	ldd	r24, Y+2	; 0x02
+ 5ca:	9b 81       	ldd	r25, Y+3	; 0x03
+ 5cc:	3c d1       	rcall	.+632    	; 0x846 <cm_setOutputMultiSynthRaw>
+ 5ce:	81 e4       	ldi	r24, 0x41	; 65
+ 5d0:	93 e0       	ldi	r25, 0x03	; 3
+ 5d2:	01 97       	sbiw	r24, 0x01	; 1
+ 5d4:	f1 f7       	brne	.-4      	; 0x5d2 <cqm_setPLLParam+0x6e>
+ 5d6:	00 00       	nop
+	_delay_ms(1);
+	cm_setCLKControl(inst->si5351_dev,output,SI5351_CLK_POWER_UP);
+ 5d8:	40 e0       	ldi	r20, 0x00	; 0
+ 5da:	69 2d       	mov	r22, r9
+ 5dc:	8a 81       	ldd	r24, Y+2	; 0x02
+ 5de:	9b 81       	ldd	r25, Y+3	; 0x03
+ 5e0:	b8 d1       	rcall	.+880    	; 0x952 <cm_setCLKControl>
 	
-	_delay_ms(100);
 	
-	cm_EEPROM_write(0x00,data_set,1);
- 124:	41 e0       	ldi	r20, 0x01	; 1
- 126:	60 e0       	ldi	r22, 0x00	; 0
- 128:	7f e3       	ldi	r23, 0x3F	; 63
- 12a:	80 e0       	ldi	r24, 0x00	; 0
- 12c:	90 e0       	ldi	r25, 0x00	; 0
- 12e:	9e df       	rcall	.-196    	; 0x6c <cm_EEPROM_write>
+}
+ 5e2:	df 91       	pop	r29
+ 5e4:	cf 91       	pop	r28
+ 5e6:	1f 91       	pop	r17
+ 5e8:	0f 91       	pop	r16
+ 5ea:	ff 90       	pop	r15
+ 5ec:	ef 90       	pop	r14
+ 5ee:	df 90       	pop	r13
+ 5f0:	cf 90       	pop	r12
+ 5f2:	bf 90       	pop	r11
+ 5f4:	af 90       	pop	r10
+ 5f6:	9f 90       	pop	r9
+ 5f8:	08 95       	ret
+
+000005fa <cqm6xx_app_loadPLLParam>:
+
+static void cqm6xx_app_loadPLLParam(storno_xtal_app_t *inst){
+ 5fa:	cf 93       	push	r28
+ 5fc:	df 93       	push	r29
+ 5fe:	ec 01       	movw	r28, r24
+	
+	cm_setInputSource(inst->si5351_dev, SI5351_CLK_SOURCE_XTAL);
+ 600:	60 e0       	ldi	r22, 0x00	; 0
+ 602:	8a 81       	ldd	r24, Y+2	; 0x02
+ 604:	9b 81       	ldd	r25, Y+3	; 0x03
+ 606:	d3 d1       	rcall	.+934    	; 0x9ae <cm_setInputSource>
+ 608:	81 e4       	ldi	r24, 0x41	; 65
+ 60a:	93 e0       	ldi	r25, 0x03	; 3
+ 60c:	01 97       	sbiw	r24, 0x01	; 1
+ 60e:	f1 f7       	brne	.-4      	; 0x60c <cqm6xx_app_loadPLLParam+0x12>
+ 610:	00 00       	nop
+	_delay_ms(1);
+
+	inst->pll_param_ptr = &temp_msg;
+ 612:	88 e4       	ldi	r24, 0x48	; 72
+ 614:	9f e3       	ldi	r25, 0x3F	; 63
+ 616:	8c 83       	std	Y+4, r24	; 0x04
+ 618:	9d 83       	std	Y+5, r25	; 0x05
+	cm_EEPROM_read(PLLA_SETTINGS_EEPROM_ADDR,msg_ptr,sizeof(storno_pll_param_msg));
+ 61a:	60 91 06 3f 	lds	r22, 0x3F06	; 0x803f06 <msg_ptr>
+ 61e:	70 91 07 3f 	lds	r23, 0x3F07	; 0x803f07 <msg_ptr+0x1>
+ 622:	49 e1       	ldi	r20, 0x19	; 25
+ 624:	80 e0       	ldi	r24, 0x00	; 0
+ 626:	90 e0       	ldi	r25, 0x00	; 0
+ 628:	3f dd       	rcall	.-1410   	; 0xa8 <cm_EEPROM_read>
+	
+	cqm_setPLLParam(inst, SI5351_PLL_A, SI5351_OUTPUT_0);
+ 62a:	40 e0       	ldi	r20, 0x00	; 0
+ 62c:	60 e0       	ldi	r22, 0x00	; 0
+ 62e:	ce 01       	movw	r24, r28
+ 630:	99 df       	rcall	.-206    	; 0x564 <cqm_setPLLParam>
+	cm_setCLKControl(inst->si5351_dev,SI5351_OUTPUT_0,SI5351_CLK_POWER_UP);
+ 632:	40 e0       	ldi	r20, 0x00	; 0
+ 634:	60 e0       	ldi	r22, 0x00	; 0
+ 636:	8a 81       	ldd	r24, Y+2	; 0x02
+ 638:	9b 81       	ldd	r25, Y+3	; 0x03
+ 63a:	8b d1       	rcall	.+790    	; 0x952 <cm_setCLKControl>
+ 63c:	81 e4       	ldi	r24, 0x41	; 65
+ 63e:	93 e0       	ldi	r25, 0x03	; 3
+ 640:	01 97       	sbiw	r24, 0x01	; 1
+ 642:	f1 f7       	brne	.-4      	; 0x640 <cqm6xx_app_loadPLLParam+0x46>
+ 644:	00 00       	nop
+	//cm_setCLKControl(inst->si5351_dev,SI5351_OUTPUT_1,SI5351_CLK_POWER_UP);
+	
+	//inst->pll_param_ptr = NULL;
+	
+	
+}
+ 646:	df 91       	pop	r29
+ 648:	cf 91       	pop	r28
+ 64a:	08 95       	ret
+
+0000064c <cqm6xx_app_updateOsc>:
+		if(inst == NULL)return 1;
+		
+		return 0;
+} 
+
+static void cqm6xx_app_updateOsc(storno_xtal_app_t *inst){
+ 64c:	cf 93       	push	r28
+ 64e:	df 93       	push	r29
+ 650:	ec 01       	movw	r28, r24
+	
+	// Check Struct
+	if(isStructValid(inst) != 0)return;
+ 652:	7b df       	rcall	.-266    	; 0x54a <isStructValid>
+ 654:	81 11       	cpse	r24, r1
+ 656:	32 c0       	rjmp	.+100    	; 0x6bc <cqm6xx_app_updateOsc+0x70>
+	
+	// We will only do this once, aka when transisioning from RX to TX and TX to RX..
+	if(inst->state_next == inst->state_now)return;
+ 658:	89 81       	ldd	r24, Y+1	; 0x01
+ 65a:	98 81       	ld	r25, Y
+ 65c:	89 17       	cp	r24, r25
+ 65e:	71 f1       	breq	.+92     	; 0x6bc <cqm6xx_app_updateOsc+0x70>
+	
+	switch(inst->state_next){
+ 660:	81 30       	cpi	r24, 0x01	; 1
+ 662:	19 f0       	breq	.+6      	; 0x66a <cqm6xx_app_updateOsc+0x1e>
+ 664:	82 30       	cpi	r24, 0x02	; 2
+ 666:	b1 f0       	breq	.+44     	; 0x694 <cqm6xx_app_updateOsc+0x48>
+ 668:	29 c0       	rjmp	.+82     	; 0x6bc <cqm6xx_app_updateOsc+0x70>
+ 66a:	81 e4       	ldi	r24, 0x41	; 65
+ 66c:	93 e0       	ldi	r25, 0x03	; 3
+ 66e:	01 97       	sbiw	r24, 0x01	; 1
+ 670:	f1 f7       	brne	.-4      	; 0x66e <cqm6xx_app_updateOsc+0x22>
+ 672:	00 00       	nop
+		
+		case STORNO_APP_RX_MODE:
+				_delay_ms(1);
+				cm_setOutputEnable(inst->si5351_dev,SI5351_OUTPUT_0,SI5351_OUTPUT_ENABLE); // RX
+ 674:	40 e0       	ldi	r20, 0x00	; 0
+ 676:	60 e0       	ldi	r22, 0x00	; 0
+ 678:	8a 81       	ldd	r24, Y+2	; 0x02
+ 67a:	9b 81       	ldd	r25, Y+3	; 0x03
+ 67c:	4a d1       	rcall	.+660    	; 0x912 <cm_setOutputEnable>
+ 67e:	81 e4       	ldi	r24, 0x41	; 65
+ 680:	93 e0       	ldi	r25, 0x03	; 3
+ 682:	01 97       	sbiw	r24, 0x01	; 1
+ 684:	f1 f7       	brne	.-4      	; 0x682 <cqm6xx_app_updateOsc+0x36>
+ 686:	00 00       	nop
+				_delay_ms(1);
+				cm_setOutputEnable(inst->si5351_dev,SI5351_OUTPUT_1,SI5351_OUTPUT_DISABLE); // TX
+ 688:	41 e0       	ldi	r20, 0x01	; 1
+ 68a:	61 e0       	ldi	r22, 0x01	; 1
+ 68c:	8a 81       	ldd	r24, Y+2	; 0x02
+ 68e:	9b 81       	ldd	r25, Y+3	; 0x03
+ 690:	40 d1       	rcall	.+640    	; 0x912 <cm_setOutputEnable>
+		
+		break;
+ 692:	14 c0       	rjmp	.+40     	; 0x6bc <cqm6xx_app_updateOsc+0x70>
+ 694:	81 e4       	ldi	r24, 0x41	; 65
+ 696:	93 e0       	ldi	r25, 0x03	; 3
+ 698:	01 97       	sbiw	r24, 0x01	; 1
+ 69a:	f1 f7       	brne	.-4      	; 0x698 <cqm6xx_app_updateOsc+0x4c>
+ 69c:	00 00       	nop
+		
+		case STORNO_APP_TX_MODE:
+				_delay_ms(1);
+				cm_setOutputEnable(inst->si5351_dev,SI5351_OUTPUT_0,SI5351_OUTPUT_DISABLE); // RX
+ 69e:	41 e0       	ldi	r20, 0x01	; 1
+ 6a0:	60 e0       	ldi	r22, 0x00	; 0
+ 6a2:	8a 81       	ldd	r24, Y+2	; 0x02
+ 6a4:	9b 81       	ldd	r25, Y+3	; 0x03
+ 6a6:	35 d1       	rcall	.+618    	; 0x912 <cm_setOutputEnable>
+ 6a8:	81 e4       	ldi	r24, 0x41	; 65
+ 6aa:	93 e0       	ldi	r25, 0x03	; 3
+ 6ac:	01 97       	sbiw	r24, 0x01	; 1
+ 6ae:	f1 f7       	brne	.-4      	; 0x6ac <cqm6xx_app_updateOsc+0x60>
+ 6b0:	00 00       	nop
+				_delay_ms(1);
+				cm_setOutputEnable(inst->si5351_dev,SI5351_OUTPUT_1,SI5351_OUTPUT_ENABLE); // TX
+ 6b2:	40 e0       	ldi	r20, 0x00	; 0
+ 6b4:	61 e0       	ldi	r22, 0x01	; 1
+ 6b6:	8a 81       	ldd	r24, Y+2	; 0x02
+ 6b8:	9b 81       	ldd	r25, Y+3	; 0x03
+ 6ba:	2b d1       	rcall	.+598    	; 0x912 <cm_setOutputEnable>
+		break;
+		
+	}
+	
+	
+}
+ 6bc:	df 91       	pop	r29
+ 6be:	cf 91       	pop	r28
+ 6c0:	08 95       	ret
+
+000006c2 <cqm6xx_app_statemachine>:
+	//inst->pll_param_ptr = NULL;
+	
+	
+}
+
+void cqm6xx_app_statemachine(storno_xtal_app_t *inst){
+ 6c2:	cf 93       	push	r28
+ 6c4:	df 93       	push	r29
+ 6c6:	ec 01       	movw	r28, r24
+	
+	// Check Struct
+	if(isStructValid(inst) != 0)return;
+ 6c8:	40 df       	rcall	.-384    	; 0x54a <isStructValid>
+ 6ca:	81 11       	cpse	r24, r1
+ 6cc:	24 c0       	rjmp	.+72     	; 0x716 <cqm6xx_app_statemachine+0x54>
+		
+	switch (inst->state_next)
+ 6ce:	89 81       	ldd	r24, Y+1	; 0x01
+ 6d0:	81 30       	cpi	r24, 0x01	; 1
+ 6d2:	51 f0       	breq	.+20     	; 0x6e8 <cqm6xx_app_statemachine+0x26>
+ 6d4:	18 f0       	brcs	.+6      	; 0x6dc <cqm6xx_app_statemachine+0x1a>
+ 6d6:	82 30       	cpi	r24, 0x02	; 2
+ 6d8:	99 f0       	breq	.+38     	; 0x700 <cqm6xx_app_statemachine+0x3e>
+ 6da:	1d c0       	rjmp	.+58     	; 0x716 <cqm6xx_app_statemachine+0x54>
+	{
+		case STORNO_APP_PROGRAM_OSC:
+			// Read PLL parameters from EEPROM and Program PLL values here:
+			inst->state_now = inst->state_next;
+ 6dc:	88 83       	st	Y, r24
+			
+			cqm6xx_app_loadPLLParam(inst);
+ 6de:	ce 01       	movw	r24, r28
+ 6e0:	8c df       	rcall	.-232    	; 0x5fa <cqm6xx_app_loadPLLParam>
+			
+			
+			// if ok, then go to RX mode:
+			inst->state_next = STORNO_APP_RX_MODE;
+ 6e2:	81 e0       	ldi	r24, 0x01	; 1
+ 6e4:	89 83       	std	Y+1, r24	; 0x01
+			break;
+ 6e6:	17 c0       	rjmp	.+46     	; 0x716 <cqm6xx_app_statemachine+0x54>
+			
+		
+		case STORNO_APP_RX_MODE: 
+			// If we just came from another state, then Enable RX osc here..
+			cqm6xx_app_updateOsc(inst);
+ 6e8:	ce 01       	movw	r24, r28
+ 6ea:	b0 df       	rcall	.-160    	; 0x64c <cqm6xx_app_updateOsc>
+			
+			// Update state now..
+			inst->state_now = inst->state_next;
+ 6ec:	89 81       	ldd	r24, Y+1	; 0x01
+ 6ee:	88 83       	st	Y, r24
+			
+			
+			// If PTT is hold, then disable RX osc, and go to STORNO_APP_TX_MODE, to enable tx osc.
+			if(gpio_get_level(GPIO_PORTA,GPIO_PIN_PTT) == GPIO_LEVEL_SET) inst->state_next = STORNO_APP_TX_MODE;
+ 6f0:	63 e0       	ldi	r22, 0x03	; 3
+ 6f2:	80 e0       	ldi	r24, 0x00	; 0
+ 6f4:	fc dc       	rcall	.-1544   	; 0xee <gpio_get_level>
+ 6f6:	01 97       	sbiw	r24, 0x01	; 1
+ 6f8:	71 f4       	brne	.+28     	; 0x716 <cqm6xx_app_statemachine+0x54>
+ 6fa:	82 e0       	ldi	r24, 0x02	; 2
+ 6fc:	89 83       	std	Y+1, r24	; 0x01
+ 6fe:	0b c0       	rjmp	.+22     	; 0x716 <cqm6xx_app_statemachine+0x54>
+			
+		break;
+		
+		case STORNO_APP_TX_MODE:
+			// If we just came from another state, then Enable TX osc here..
+			cqm6xx_app_updateOsc(inst);
+ 700:	ce 01       	movw	r24, r28
+ 702:	a4 df       	rcall	.-184    	; 0x64c <cqm6xx_app_updateOsc>
+			
+			// Update state now..
+			inst->state_now = inst->state_next;
+ 704:	89 81       	ldd	r24, Y+1	; 0x01
+ 706:	88 83       	st	Y, r24
+			
+			// If PTT is released, then disable TX osc, and go to STORNO_APP_RX_MODE, to enable rx osc.
+			if(gpio_get_level(GPIO_PORTA,GPIO_PIN_PTT) == GPIO_LEVEL_RESET) inst->state_next = STORNO_APP_RX_MODE;
+ 708:	63 e0       	ldi	r22, 0x03	; 3
+ 70a:	80 e0       	ldi	r24, 0x00	; 0
+ 70c:	f0 dc       	rcall	.-1568   	; 0xee <gpio_get_level>
+ 70e:	89 2b       	or	r24, r25
+ 710:	11 f4       	brne	.+4      	; 0x716 <cqm6xx_app_statemachine+0x54>
+ 712:	81 e0       	ldi	r24, 0x01	; 1
+ 714:	89 83       	std	Y+1, r24	; 0x01
+		default:
+		break;
+	}
+	
+	
+}
+ 716:	df 91       	pop	r29
+ 718:	cf 91       	pop	r28
+ 71a:	08 95       	ret
+
+0000071c <programPLL_Parameters>:
+
+void programPLL_Parameters(storno_xtal_app_t *inst){
+	
+	//Burn settings into eeprom here:
+	switch(inst->pll_param_ptr->PLL_Ident){
+ 71c:	fc 01       	movw	r30, r24
+ 71e:	64 81       	ldd	r22, Z+4	; 0x04
+ 720:	75 81       	ldd	r23, Z+5	; 0x05
+ 722:	fb 01       	movw	r30, r22
+ 724:	80 81       	ld	r24, Z
+ 726:	88 23       	and	r24, r24
+ 728:	19 f0       	breq	.+6      	; 0x730 <programPLL_Parameters+0x14>
+ 72a:	81 30       	cpi	r24, 0x01	; 1
+ 72c:	31 f0       	breq	.+12     	; 0x73a <programPLL_Parameters+0x1e>
+ 72e:	08 95       	ret
+		
+		case MSG_PLLA_PARAM:
+			cm_EEPROM_write(PLLA_SETTINGS_EEPROM_ADDR,(uint8_t*)(inst->pll_param_ptr), sizeof(storno_pll_param_msg));	
+ 730:	49 e1       	ldi	r20, 0x19	; 25
+ 732:	80 e0       	ldi	r24, 0x00	; 0
+ 734:	90 e0       	ldi	r25, 0x00	; 0
+ 736:	9a dc       	rcall	.-1740   	; 0x6c <cm_EEPROM_write>
+		break;
+ 738:	08 95       	ret
+		
+		case MSG_PLLB_PARAM:
+			cm_EEPROM_write(PLLB_SETTINGS_EEPROM_ADDR,(uint8_t*)(inst->pll_param_ptr), sizeof(storno_pll_param_msg));
+ 73a:	49 e1       	ldi	r20, 0x19	; 25
+ 73c:	80 e2       	ldi	r24, 0x20	; 32
+ 73e:	90 e0       	ldi	r25, 0x00	; 0
+ 740:	95 dc       	rcall	.-1750   	; 0x6c <cm_EEPROM_write>
+ 742:	08 95       	ret
+
+00000744 <uart_rx_event>:
+	
+}
+
+int uart_rx_event(storno_xtal_app_t *inst, void *rxData){
+	
+	inst->pll_param_ptr = rxData;
+ 744:	fc 01       	movw	r30, r24
+ 746:	64 83       	std	Z+4, r22	; 0x04
+ 748:	75 83       	std	Z+5, r23	; 0x05
+	
+	programPLL_Parameters(inst);
+ 74a:	e8 df       	rcall	.-48     	; 0x71c <programPLL_Parameters>
+	
+	return 0;
+	
+}
+ 74c:	80 e0       	ldi	r24, 0x00	; 0
+ 74e:	90 e0       	ldi	r25, 0x00	; 0
+ 750:	08 95       	ret
+
+00000752 <cqm6xx_app_init>:
+
+void cqm6xx_app_init(storno_xtal_app_t *inst, void *si5351_dev){
+ 752:	cf 93       	push	r28
+ 754:	df 93       	push	r29
+	
+	if(si5351_dev == NULL) return;
+ 756:	61 15       	cp	r22, r1
+ 758:	71 05       	cpc	r23, r1
+ 75a:	71 f0       	breq	.+28     	; 0x778 <cqm6xx_app_init+0x26>
+	if(inst == NULL)return;
+ 75c:	00 97       	sbiw	r24, 0x00	; 0
+ 75e:	61 f0       	breq	.+24     	; 0x778 <cqm6xx_app_init+0x26>
+ 760:	ec 01       	movw	r28, r24
+	
+	inst->state_next = STORNO_APP_PROGRAM_OSC;
+ 762:	19 82       	std	Y+1, r1	; 0x01
+	inst->state_now = STORNO_APP_PROGRAM_OSC;
+ 764:	18 82       	st	Y, r1
+	
+	inst->si5351_dev = si5351_dev;
+ 766:	6a 83       	std	Y+2, r22	; 0x02
+ 768:	7b 83       	std	Y+3, r23	; 0x03
+	
+	//cm_uart_init(inst,(get_UART_Event_fpt)uart_rx_event);
+	cm_MsgCompleteEvt_Register(inst,(Get_msgComplete_Event_fpt)uart_rx_event);
+ 76a:	62 ea       	ldi	r22, 0xA2	; 162
+ 76c:	73 e0       	ldi	r23, 0x03	; 3
+ 76e:	df de       	rcall	.-578    	; 0x52e <cm_MsgCompleteEvt_Register>
+	cm_uart_init(inst,(get_UART_Event_fpt)cm_msg_DecodeMsg_Byte);
+ 770:	63 e4       	ldi	r22, 0x43	; 67
+ 772:	72 e0       	ldi	r23, 0x02	; 2
+ 774:	ce 01       	movw	r24, r28
+ 776:	08 de       	rcall	.-1008   	; 0x388 <cm_uart_init>
+	
+ 778:	df 91       	pop	r29
+ 77a:	cf 91       	pop	r28
+ 77c:	08 95       	ret
+
+0000077e <main>:
+	uint8_t data_set[25] = {0x55,56};
+	//cm_EEPROM_write(0x00,data_set,1);
+	uint8_t data[25] = {0};
+		
+int main(void)
+{
+ 77e:	cf 93       	push	r28
+ 780:	df 93       	push	r29
+ 782:	cd b7       	in	r28, 0x3d	; 61
+ 784:	de b7       	in	r29, 0x3e	; 62
+ 786:	cb 55       	subi	r28, 0x5B	; 91
+ 788:	d1 09       	sbc	r29, r1
+ 78a:	cd bf       	out	0x3d, r28	; 61
+ 78c:	de bf       	out	0x3e, r29	; 62
+    /* Replace with your application code */
+
+		// Init Periphials
+		cm_i2c_init(NULL);
+ 78e:	80 e0       	ldi	r24, 0x00	; 0
+ 790:	90 e0       	ldi	r25, 0x00	; 0
+ 792:	7d dd       	rcall	.-1286   	; 0x28e <cm_i2c_init>
+		
+		// Add devices
+		cm_i2c_device_t si5351_i2c;
+		cm_i2c_addDev(&si5351_i2c,NULL,0x60);
+ 794:	40 e6       	ldi	r20, 0x60	; 96
+ 796:	60 e0       	ldi	r22, 0x00	; 0
+ 798:	70 e0       	ldi	r23, 0x00	; 0
+ 79a:	ce 01       	movw	r24, r28
+ 79c:	01 96       	adiw	r24, 0x01	; 1
+ 79e:	91 dd       	rcall	.-1246   	; 0x2c2 <cm_i2c_addDev>
+		
+		// Init Devices:
+		si5351_driver si5351_dev;
+		cm_si5351_init(&si5351_dev,&si5351_i2c,(setGet_I2C_Event_fpt)cm_i2c_transfer);
+ 7a0:	4f e7       	ldi	r20, 0x7F	; 127
+ 7a2:	51 e0       	ldi	r21, 0x01	; 1
+ 7a4:	be 01       	movw	r22, r28
+ 7a6:	6f 5f       	subi	r22, 0xFF	; 255
+ 7a8:	7f 4f       	sbci	r23, 0xFF	; 255
+ 7aa:	ce 01       	movw	r24, r28
+ 7ac:	04 96       	adiw	r24, 0x04	; 4
+ 7ae:	a0 d1       	rcall	.+832    	; 0xaf0 <cm_si5351_init>
+		
+		cqm6xx_app_init(&storno_xtal_app, &si5351_dev);
+ 7b0:	be 01       	movw	r22, r28
+ 7b2:	6c 5f       	subi	r22, 0xFC	; 252
+ 7b4:	7f 4f       	sbci	r23, 0xFF	; 255
+ 7b6:	81 e6       	ldi	r24, 0x61	; 97
+ 7b8:	9f e3       	ldi	r25, 0x3F	; 63
+ 7ba:	cb df       	rcall	.-106    	; 0x752 <cqm6xx_app_init>
+		
 
     while (1) 
     {
 
-		//cqm6xx_app_statemachine(&storno_xtal_app);
-	if(PORTA.IN == 0x0d){
- 130:	80 91 08 04 	lds	r24, 0x0408	; 0x800408 <__RODATA_PM_OFFSET__+0x7f8408>
- 134:	8d 30       	cpi	r24, 0x0D	; 13
- 136:	59 f4       	brne	.+22     	; 0x14e <main+0x46>
-	
-		static volatile uint8_t counter = 0;
-		
-		counter++;
- 138:	80 91 1c 3f 	lds	r24, 0x3F1C	; 0x803f1c <counter.3520>
- 13c:	8f 5f       	subi	r24, 0xFF	; 255
- 13e:	80 93 1c 3f 	sts	0x3F1C, r24	; 0x803f1c <counter.3520>
-		
-		if (counter >= 50)
- 142:	80 91 1c 3f 	lds	r24, 0x3F1C	; 0x803f1c <counter.3520>
- 146:	82 33       	cpi	r24, 0x32	; 50
- 148:	10 f0       	brcs	.+4      	; 0x14e <main+0x46>
-		{
-			counter = 0;
- 14a:	10 92 1c 3f 	sts	0x3F1C, r1	; 0x803f1c <counter.3520>
- 14e:	2a e6       	ldi	r18, 0x6A	; 106
- 150:	84 e0       	ldi	r24, 0x04	; 4
- 152:	91 e0       	ldi	r25, 0x01	; 1
- 154:	21 50       	subi	r18, 0x01	; 1
- 156:	80 40       	sbci	r24, 0x00	; 0
- 158:	90 40       	sbci	r25, 0x00	; 0
- 15a:	e1 f7       	brne	.-8      	; 0x154 <main+0x4c>
- 15c:	00 c0       	rjmp	.+0      	; 0x15e <main+0x56>
- 15e:	e8 cf       	rjmp	.-48     	; 0x130 <main+0x28>
+		cqm6xx_app_statemachine(&storno_xtal_app);
+ 7bc:	81 e6       	ldi	r24, 0x61	; 97
+ 7be:	9f e3       	ldi	r25, 0x3F	; 63
+ 7c0:	80 df       	rcall	.-256    	; 0x6c2 <cqm6xx_app_statemachine>
+ 7c2:	2a e6       	ldi	r18, 0x6A	; 106
+ 7c4:	84 e0       	ldi	r24, 0x04	; 4
+ 7c6:	91 e0       	ldi	r25, 0x01	; 1
+ 7c8:	21 50       	subi	r18, 0x01	; 1
+ 7ca:	80 40       	sbci	r24, 0x00	; 0
+ 7cc:	90 40       	sbci	r25, 0x00	; 0
+ 7ce:	e1 f7       	brne	.-8      	; 0x7c8 <main+0x4a>
+ 7d0:	00 c0       	rjmp	.+0      	; 0x7d2 <main+0x54>
+ 7d2:	f4 cf       	rjmp	.-24     	; 0x7bc <main+0x3e>
 
-00000160 <eeprom_read_byte>:
- 160:	03 d0       	rcall	.+6      	; 0x168 <eeprom_mapen>
- 162:	80 81       	ld	r24, Z
- 164:	99 27       	eor	r25, r25
- 166:	08 95       	ret
+000007d4 <writeRegister>:
 
-00000168 <eeprom_mapen>:
- 168:	fc 01       	movw	r30, r24
- 16a:	e0 50       	subi	r30, 0x00	; 0
- 16c:	fc 4e       	sbci	r31, 0xEC	; 236
- 16e:	08 95       	ret
+	// Read Device Status register:
+	readRegister(inst,0x00, (uint8_t *) &inst->device_data.deviceStatus, sizeof(si5351_deviceStat_t));
 
-00000170 <eeprom_write_byte>:
- 170:	26 2f       	mov	r18, r22
+	return inst->device_data.deviceStatus.REVID;
+}
+ 7d4:	8f 92       	push	r8
+ 7d6:	9f 92       	push	r9
+ 7d8:	af 92       	push	r10
+ 7da:	bf 92       	push	r11
+ 7dc:	cf 92       	push	r12
+ 7de:	df 92       	push	r13
+ 7e0:	ef 92       	push	r14
+ 7e2:	ff 92       	push	r15
+ 7e4:	0f 93       	push	r16
+ 7e6:	1f 93       	push	r17
+ 7e8:	cf 93       	push	r28
+ 7ea:	df 93       	push	r29
+ 7ec:	ec 01       	movw	r28, r24
+ 7ee:	86 2e       	mov	r8, r22
+ 7f0:	5a 01       	movw	r10, r20
+ 7f2:	68 01       	movw	r12, r16
+ 7f4:	79 01       	movw	r14, r18
+ 7f6:	c8 01       	movw	r24, r16
+ 7f8:	01 96       	adiw	r24, 0x01	; 1
+ 7fa:	1b d2       	rcall	.+1078   	; 0xc32 <malloc>
+ 7fc:	98 2e       	mov	r9, r24
+ 7fe:	19 2f       	mov	r17, r25
+ 800:	fc 01       	movw	r30, r24
+ 802:	81 92       	st	Z+, r8
+ 804:	cf 01       	movw	r24, r30
+ 806:	a6 01       	movw	r20, r12
+ 808:	b5 01       	movw	r22, r10
+ 80a:	34 d3       	rcall	.+1640   	; 0xe74 <memcpy>
+ 80c:	ea 81       	ldd	r30, Y+2	; 0x02
+ 80e:	fb 81       	ldd	r31, Y+3	; 0x03
+ 810:	a7 01       	movw	r20, r14
+ 812:	96 01       	movw	r18, r12
+ 814:	2f 5f       	subi	r18, 0xFF	; 255
+ 816:	3f 4f       	sbci	r19, 0xFF	; 255
+ 818:	4f 4f       	sbci	r20, 0xFF	; 255
+ 81a:	5f 4f       	sbci	r21, 0xFF	; 255
+ 81c:	01 e0       	ldi	r16, 0x01	; 1
+ 81e:	69 2d       	mov	r22, r9
+ 820:	71 2f       	mov	r23, r17
+ 822:	88 81       	ld	r24, Y
+ 824:	99 81       	ldd	r25, Y+1	; 0x01
+ 826:	09 95       	icall
+ 828:	80 e0       	ldi	r24, 0x00	; 0
+ 82a:	90 e0       	ldi	r25, 0x00	; 0
+ 82c:	df 91       	pop	r29
+ 82e:	cf 91       	pop	r28
+ 830:	1f 91       	pop	r17
+ 832:	0f 91       	pop	r16
+ 834:	ff 90       	pop	r15
+ 836:	ef 90       	pop	r14
+ 838:	df 90       	pop	r13
+ 83a:	cf 90       	pop	r12
+ 83c:	bf 90       	pop	r11
+ 83e:	af 90       	pop	r10
+ 840:	9f 90       	pop	r9
+ 842:	8f 90       	pop	r8
+ 844:	08 95       	ret
 
-00000172 <eeprom_write_r18>:
- 172:	af 93       	push	r26
- 174:	bf 93       	push	r27
- 176:	e0 e0       	ldi	r30, 0x00	; 0
- 178:	f0 e1       	ldi	r31, 0x10	; 16
- 17a:	32 81       	ldd	r19, Z+2	; 0x02
- 17c:	31 fd       	sbrc	r19, 1
- 17e:	fd cf       	rjmp	.-6      	; 0x17a <eeprom_write_r18+0x8>
- 180:	dc 01       	movw	r26, r24
- 182:	a0 50       	subi	r26, 0x00	; 0
- 184:	bc 4e       	sbci	r27, 0xEC	; 236
- 186:	2c 93       	st	X, r18
- 188:	2d e9       	ldi	r18, 0x9D	; 157
- 18a:	24 bf       	out	0x34, r18	; 52
- 18c:	23 e0       	ldi	r18, 0x03	; 3
- 18e:	20 83       	st	Z, r18
- 190:	01 96       	adiw	r24, 0x01	; 1
- 192:	bf 91       	pop	r27
- 194:	af 91       	pop	r26
- 196:	08 95       	ret
+00000846 <cm_setOutputMultiSynthRaw>:
+ 846:	af 92       	push	r10
+ 848:	bf 92       	push	r11
+ 84a:	cf 92       	push	r12
+ 84c:	df 92       	push	r13
+ 84e:	ef 92       	push	r14
+ 850:	ff 92       	push	r15
+ 852:	0f 93       	push	r16
+ 854:	1f 93       	push	r17
+ 856:	fc 01       	movw	r30, r24
+ 858:	66 23       	and	r22, r22
+ 85a:	19 f0       	breq	.+6      	; 0x862 <cm_setOutputMultiSynthRaw+0x1c>
+ 85c:	61 30       	cpi	r22, 0x01	; 1
+ 85e:	41 f1       	breq	.+80     	; 0x8b0 <cm_setOutputMultiSynthRaw+0x6a>
+ 860:	4d c0       	rjmp	.+154    	; 0x8fc <cm_setOutputMultiSynthRaw+0xb6>
+ 862:	43 70       	andi	r20, 0x03	; 3
+ 864:	86 a1       	ldd	r24, Z+38	; 0x26
+ 866:	8c 7f       	andi	r24, 0xFC	; 252
+ 868:	48 2b       	or	r20, r24
+ 86a:	46 a3       	std	Z+38, r20	; 0x26
+ 86c:	37 a3       	std	Z+39, r19	; 0x27
+ 86e:	20 a7       	std	Z+40, r18	; 0x28
+ 870:	f2 a6       	std	Z+42, r15	; 0x2a
+ 872:	e3 a6       	std	Z+43, r14	; 0x2b
+ 874:	d6 01       	movw	r26, r12
+ 876:	c5 01       	movw	r24, r10
+ 878:	07 2e       	mov	r0, r23
+ 87a:	7c e0       	ldi	r23, 0x0C	; 12
+ 87c:	b6 95       	lsr	r27
+ 87e:	a7 95       	ror	r26
+ 880:	97 95       	ror	r25
+ 882:	87 95       	ror	r24
+ 884:	7a 95       	dec	r23
+ 886:	d1 f7       	brne	.-12     	; 0x87c <cm_setOutputMultiSynthRaw+0x36>
+ 888:	70 2d       	mov	r23, r0
+ 88a:	83 70       	andi	r24, 0x03	; 3
+ 88c:	82 95       	swap	r24
+ 88e:	80 7f       	andi	r24, 0xF0	; 240
+ 890:	03 70       	andi	r16, 0x03	; 3
+ 892:	80 2b       	or	r24, r16
+ 894:	81 a7       	std	Z+41, r24	; 0x29
+ 896:	b4 a2       	std	Z+36, r11	; 0x24
+ 898:	a5 a2       	std	Z+37, r10	; 0x25
+ 89a:	af 01       	movw	r20, r30
+ 89c:	4c 5d       	subi	r20, 0xDC	; 220
+ 89e:	5f 4f       	sbci	r21, 0xFF	; 255
+ 8a0:	08 e0       	ldi	r16, 0x08	; 8
+ 8a2:	10 e0       	ldi	r17, 0x00	; 0
+ 8a4:	20 e0       	ldi	r18, 0x00	; 0
+ 8a6:	30 e0       	ldi	r19, 0x00	; 0
+ 8a8:	6a e2       	ldi	r22, 0x2A	; 42
+ 8aa:	cf 01       	movw	r24, r30
+ 8ac:	93 df       	rcall	.-218    	; 0x7d4 <writeRegister>
+ 8ae:	26 c0       	rjmp	.+76     	; 0x8fc <cm_setOutputMultiSynthRaw+0xb6>
+ 8b0:	43 70       	andi	r20, 0x03	; 3
+ 8b2:	86 a5       	ldd	r24, Z+46	; 0x2e
+ 8b4:	8c 7f       	andi	r24, 0xFC	; 252
+ 8b6:	48 2b       	or	r20, r24
+ 8b8:	46 a7       	std	Z+46, r20	; 0x2e
+ 8ba:	37 a7       	std	Z+47, r19	; 0x2f
+ 8bc:	20 ab       	std	Z+48, r18	; 0x30
+ 8be:	f2 aa       	std	Z+50, r15	; 0x32
+ 8c0:	e3 aa       	std	Z+51, r14	; 0x33
+ 8c2:	d6 01       	movw	r26, r12
+ 8c4:	c5 01       	movw	r24, r10
+ 8c6:	07 2e       	mov	r0, r23
+ 8c8:	7c e0       	ldi	r23, 0x0C	; 12
+ 8ca:	b6 95       	lsr	r27
+ 8cc:	a7 95       	ror	r26
+ 8ce:	97 95       	ror	r25
+ 8d0:	87 95       	ror	r24
+ 8d2:	7a 95       	dec	r23
+ 8d4:	d1 f7       	brne	.-12     	; 0x8ca <cm_setOutputMultiSynthRaw+0x84>
+ 8d6:	70 2d       	mov	r23, r0
+ 8d8:	83 70       	andi	r24, 0x03	; 3
+ 8da:	82 95       	swap	r24
+ 8dc:	80 7f       	andi	r24, 0xF0	; 240
+ 8de:	03 70       	andi	r16, 0x03	; 3
+ 8e0:	80 2b       	or	r24, r16
+ 8e2:	81 ab       	std	Z+49, r24	; 0x31
+ 8e4:	b4 a6       	std	Z+44, r11	; 0x2c
+ 8e6:	a5 a6       	std	Z+45, r10	; 0x2d
+ 8e8:	af 01       	movw	r20, r30
+ 8ea:	44 5d       	subi	r20, 0xD4	; 212
+ 8ec:	5f 4f       	sbci	r21, 0xFF	; 255
+ 8ee:	08 e0       	ldi	r16, 0x08	; 8
+ 8f0:	10 e0       	ldi	r17, 0x00	; 0
+ 8f2:	20 e0       	ldi	r18, 0x00	; 0
+ 8f4:	30 e0       	ldi	r19, 0x00	; 0
+ 8f6:	62 e3       	ldi	r22, 0x32	; 50
+ 8f8:	cf 01       	movw	r24, r30
+ 8fa:	6c df       	rcall	.-296    	; 0x7d4 <writeRegister>
+ 8fc:	80 e0       	ldi	r24, 0x00	; 0
+ 8fe:	90 e0       	ldi	r25, 0x00	; 0
+ 900:	1f 91       	pop	r17
+ 902:	0f 91       	pop	r16
+ 904:	ff 90       	pop	r15
+ 906:	ef 90       	pop	r14
+ 908:	df 90       	pop	r13
+ 90a:	cf 90       	pop	r12
+ 90c:	bf 90       	pop	r11
+ 90e:	af 90       	pop	r10
+ 910:	08 95       	ret
 
-00000198 <_exit>:
- 198:	f8 94       	cli
+00000912 <cm_setOutputEnable>:
+ 912:	0f 93       	push	r16
+ 914:	1f 93       	push	r17
+ 916:	66 23       	and	r22, r22
+ 918:	19 f0       	breq	.+6      	; 0x920 <cm_setOutputEnable+0xe>
+ 91a:	61 30       	cpi	r22, 0x01	; 1
+ 91c:	39 f0       	breq	.+14     	; 0x92c <cm_setOutputEnable+0x1a>
+ 91e:	0b c0       	rjmp	.+22     	; 0x936 <cm_setOutputEnable+0x24>
+ 920:	fc 01       	movw	r30, r24
+ 922:	27 81       	ldd	r18, Z+7	; 0x07
+ 924:	40 fb       	bst	r20, 0
+ 926:	20 f9       	bld	r18, 0
+ 928:	27 83       	std	Z+7, r18	; 0x07
+ 92a:	05 c0       	rjmp	.+10     	; 0x936 <cm_setOutputEnable+0x24>
+ 92c:	fc 01       	movw	r30, r24
+ 92e:	27 81       	ldd	r18, Z+7	; 0x07
+ 930:	40 fb       	bst	r20, 0
+ 932:	21 f9       	bld	r18, 1
+ 934:	27 83       	std	Z+7, r18	; 0x07
+ 936:	ac 01       	movw	r20, r24
+ 938:	49 5f       	subi	r20, 0xF9	; 249
+ 93a:	5f 4f       	sbci	r21, 0xFF	; 255
+ 93c:	01 e0       	ldi	r16, 0x01	; 1
+ 93e:	10 e0       	ldi	r17, 0x00	; 0
+ 940:	20 e0       	ldi	r18, 0x00	; 0
+ 942:	30 e0       	ldi	r19, 0x00	; 0
+ 944:	63 e0       	ldi	r22, 0x03	; 3
+ 946:	46 df       	rcall	.-372    	; 0x7d4 <writeRegister>
+ 948:	80 e0       	ldi	r24, 0x00	; 0
+ 94a:	90 e0       	ldi	r25, 0x00	; 0
+ 94c:	1f 91       	pop	r17
+ 94e:	0f 91       	pop	r16
+ 950:	08 95       	ret
 
-0000019a <__stop_program>:
- 19a:	ff cf       	rjmp	.-2      	; 0x19a <__stop_program>
+00000952 <cm_setCLKControl>:
+ 952:	0f 93       	push	r16
+ 954:	1f 93       	push	r17
+ 956:	66 23       	and	r22, r22
+ 958:	19 f0       	breq	.+6      	; 0x960 <cm_setCLKControl+0xe>
+ 95a:	61 30       	cpi	r22, 0x01	; 1
+ 95c:	a1 f0       	breq	.+40     	; 0x986 <cm_setCLKControl+0x34>
+ 95e:	22 c0       	rjmp	.+68     	; 0x9a4 <cm_setCLKControl+0x52>
+ 960:	fc 01       	movw	r30, r24
+ 962:	22 85       	ldd	r18, Z+10	; 0x0a
+ 964:	40 fb       	bst	r20, 0
+ 966:	27 f9       	bld	r18, 7
+ 968:	33 85       	ldd	r19, Z+11	; 0x0b
+ 96a:	3f 7d       	andi	r19, 0xDF	; 223
+ 96c:	33 87       	std	Z+11, r19	; 0x0b
+ 96e:	2f 64       	ori	r18, 0x4F	; 79
+ 970:	22 87       	std	Z+10, r18	; 0x0a
+ 972:	ac 01       	movw	r20, r24
+ 974:	46 5f       	subi	r20, 0xF6	; 246
+ 976:	5f 4f       	sbci	r21, 0xFF	; 255
+ 978:	01 e0       	ldi	r16, 0x01	; 1
+ 97a:	10 e0       	ldi	r17, 0x00	; 0
+ 97c:	20 e0       	ldi	r18, 0x00	; 0
+ 97e:	30 e0       	ldi	r19, 0x00	; 0
+ 980:	60 e1       	ldi	r22, 0x10	; 16
+ 982:	28 df       	rcall	.-432    	; 0x7d4 <writeRegister>
+ 984:	0f c0       	rjmp	.+30     	; 0x9a4 <cm_setCLKControl+0x52>
+ 986:	fc 01       	movw	r30, r24
+ 988:	23 85       	ldd	r18, Z+11	; 0x0b
+ 98a:	40 fb       	bst	r20, 0
+ 98c:	27 f9       	bld	r18, 7
+ 98e:	2f 66       	ori	r18, 0x6F	; 111
+ 990:	23 87       	std	Z+11, r18	; 0x0b
+ 992:	ac 01       	movw	r20, r24
+ 994:	45 5f       	subi	r20, 0xF5	; 245
+ 996:	5f 4f       	sbci	r21, 0xFF	; 255
+ 998:	01 e0       	ldi	r16, 0x01	; 1
+ 99a:	10 e0       	ldi	r17, 0x00	; 0
+ 99c:	20 e0       	ldi	r18, 0x00	; 0
+ 99e:	30 e0       	ldi	r19, 0x00	; 0
+ 9a0:	61 e1       	ldi	r22, 0x11	; 17
+ 9a2:	18 df       	rcall	.-464    	; 0x7d4 <writeRegister>
+ 9a4:	80 e0       	ldi	r24, 0x00	; 0
+ 9a6:	90 e0       	ldi	r25, 0x00	; 0
+ 9a8:	1f 91       	pop	r17
+ 9aa:	0f 91       	pop	r16
+ 9ac:	08 95       	ret
+
+000009ae <cm_setInputSource>:
+ 9ae:	0f 93       	push	r16
+ 9b0:	1f 93       	push	r17
+ 9b2:	66 23       	and	r22, r22
+ 9b4:	19 f0       	breq	.+6      	; 0x9bc <cm_setInputSource+0xe>
+ 9b6:	61 30       	cpi	r22, 0x01	; 1
+ 9b8:	39 f0       	breq	.+14     	; 0x9c8 <cm_setInputSource+0x1a>
+ 9ba:	0a c0       	rjmp	.+20     	; 0x9d0 <cm_setInputSource+0x22>
+ 9bc:	fc 01       	movw	r30, r24
+ 9be:	21 85       	ldd	r18, Z+9	; 0x09
+ 9c0:	2b 7f       	andi	r18, 0xFB	; 251
+ 9c2:	27 7f       	andi	r18, 0xF7	; 247
+ 9c4:	21 87       	std	Z+9, r18	; 0x09
+ 9c6:	04 c0       	rjmp	.+8      	; 0x9d0 <cm_setInputSource+0x22>
+ 9c8:	fc 01       	movw	r30, r24
+ 9ca:	21 85       	ldd	r18, Z+9	; 0x09
+ 9cc:	24 60       	ori	r18, 0x04	; 4
+ 9ce:	21 87       	std	Z+9, r18	; 0x09
+ 9d0:	ac 01       	movw	r20, r24
+ 9d2:	47 5f       	subi	r20, 0xF7	; 247
+ 9d4:	5f 4f       	sbci	r21, 0xFF	; 255
+ 9d6:	01 e0       	ldi	r16, 0x01	; 1
+ 9d8:	10 e0       	ldi	r17, 0x00	; 0
+ 9da:	20 e0       	ldi	r18, 0x00	; 0
+ 9dc:	30 e0       	ldi	r19, 0x00	; 0
+ 9de:	60 ef       	ldi	r22, 0xF0	; 240
+ 9e0:	f9 de       	rcall	.-526    	; 0x7d4 <writeRegister>
+ 9e2:	80 e0       	ldi	r24, 0x00	; 0
+ 9e4:	90 e0       	ldi	r25, 0x00	; 0
+ 9e6:	1f 91       	pop	r17
+ 9e8:	0f 91       	pop	r16
+ 9ea:	08 95       	ret
+
+000009ec <cm_resetPLLs>:
+ 9ec:	0f 93       	push	r16
+ 9ee:	1f 93       	push	r17
+ 9f0:	31 e0       	ldi	r19, 0x01	; 1
+ 9f2:	61 11       	cpse	r22, r1
+ 9f4:	01 c0       	rjmp	.+2      	; 0x9f8 <cm_resetPLLs+0xc>
+ 9f6:	30 e0       	ldi	r19, 0x00	; 0
+ 9f8:	fc 01       	movw	r30, r24
+ 9fa:	e9 5a       	subi	r30, 0xA9	; 169
+ 9fc:	ff 4f       	sbci	r31, 0xFF	; 255
+ 9fe:	20 81       	ld	r18, Z
+ a00:	30 fb       	bst	r19, 0
+ a02:	25 f9       	bld	r18, 5
+ a04:	20 83       	st	Z, r18
+ a06:	31 e0       	ldi	r19, 0x01	; 1
+ a08:	41 11       	cpse	r20, r1
+ a0a:	01 c0       	rjmp	.+2      	; 0xa0e <cm_resetPLLs+0x22>
+ a0c:	30 e0       	ldi	r19, 0x00	; 0
+ a0e:	ac 01       	movw	r20, r24
+ a10:	49 5a       	subi	r20, 0xA9	; 169
+ a12:	5f 4f       	sbci	r21, 0xFF	; 255
+ a14:	fa 01       	movw	r30, r20
+ a16:	20 81       	ld	r18, Z
+ a18:	30 fb       	bst	r19, 0
+ a1a:	27 f9       	bld	r18, 7
+ a1c:	20 83       	st	Z, r18
+ a1e:	01 e0       	ldi	r16, 0x01	; 1
+ a20:	10 e0       	ldi	r17, 0x00	; 0
+ a22:	20 e0       	ldi	r18, 0x00	; 0
+ a24:	30 e0       	ldi	r19, 0x00	; 0
+ a26:	61 eb       	ldi	r22, 0xB1	; 177
+ a28:	d5 de       	rcall	.-598    	; 0x7d4 <writeRegister>
+ a2a:	80 e0       	ldi	r24, 0x00	; 0
+ a2c:	90 e0       	ldi	r25, 0x00	; 0
+ a2e:	1f 91       	pop	r17
+ a30:	0f 91       	pop	r16
+ a32:	08 95       	ret
+
+00000a34 <cm_setPllParamRaw>:
+ a34:	af 92       	push	r10
+ a36:	bf 92       	push	r11
+ a38:	cf 92       	push	r12
+ a3a:	df 92       	push	r13
+ a3c:	ef 92       	push	r14
+ a3e:	ff 92       	push	r15
+ a40:	0f 93       	push	r16
+ a42:	1f 93       	push	r17
+ a44:	cf 93       	push	r28
+ a46:	df 93       	push	r29
+ a48:	ec 01       	movw	r28, r24
+ a4a:	66 23       	and	r22, r22
+ a4c:	19 f0       	breq	.+6      	; 0xa54 <cm_setPllParamRaw+0x20>
+ a4e:	61 30       	cpi	r22, 0x01	; 1
+ a50:	01 f1       	breq	.+64     	; 0xa92 <cm_setPllParamRaw+0x5e>
+ a52:	3d c0       	rjmp	.+122    	; 0xace <cm_setPllParamRaw+0x9a>
+ a54:	42 70       	andi	r20, 0x02	; 2
+ a56:	8e 89       	ldd	r24, Y+22	; 0x16
+ a58:	8c 7f       	andi	r24, 0xFC	; 252
+ a5a:	48 2b       	or	r20, r24
+ a5c:	4e 8b       	std	Y+22, r20	; 0x16
+ a5e:	3f 8b       	std	Y+23, r19	; 0x17
+ a60:	28 8f       	std	Y+24, r18	; 0x18
+ a62:	d8 01       	movw	r26, r16
+ a64:	c7 01       	movw	r24, r14
+ a66:	88 27       	eor	r24, r24
+ a68:	99 27       	eor	r25, r25
+ a6a:	af 70       	andi	r26, 0x0F	; 15
+ a6c:	bb 27       	eor	r27, r27
+ a6e:	fa 8e       	std	Y+26, r15	; 0x1a
+ a70:	eb 8e       	std	Y+27, r14	; 0x1b
+ a72:	8a 2f       	mov	r24, r26
+ a74:	8f 70       	andi	r24, 0x0F	; 15
+ a76:	89 8f       	std	Y+25, r24	; 0x19
+ a78:	bc 8a       	std	Y+20, r11	; 0x14
+ a7a:	ad 8a       	std	Y+21, r10	; 0x15
+ a7c:	08 e0       	ldi	r16, 0x08	; 8
+ a7e:	10 e0       	ldi	r17, 0x00	; 0
+ a80:	20 e0       	ldi	r18, 0x00	; 0
+ a82:	30 e0       	ldi	r19, 0x00	; 0
+ a84:	ae 01       	movw	r20, r28
+ a86:	4c 5e       	subi	r20, 0xEC	; 236
+ a88:	5f 4f       	sbci	r21, 0xFF	; 255
+ a8a:	6a e1       	ldi	r22, 0x1A	; 26
+ a8c:	ce 01       	movw	r24, r28
+ a8e:	a2 de       	rcall	.-700    	; 0x7d4 <writeRegister>
+ a90:	1e c0       	rjmp	.+60     	; 0xace <cm_setPllParamRaw+0x9a>
+ a92:	42 70       	andi	r20, 0x02	; 2
+ a94:	8e 8d       	ldd	r24, Y+30	; 0x1e
+ a96:	8c 7f       	andi	r24, 0xFC	; 252
+ a98:	48 2b       	or	r20, r24
+ a9a:	4e 8f       	std	Y+30, r20	; 0x1e
+ a9c:	3f 8f       	std	Y+31, r19	; 0x1f
+ a9e:	28 a3       	std	Y+32, r18	; 0x20
+ aa0:	d8 01       	movw	r26, r16
+ aa2:	c7 01       	movw	r24, r14
+ aa4:	88 27       	eor	r24, r24
+ aa6:	99 27       	eor	r25, r25
+ aa8:	af 70       	andi	r26, 0x0F	; 15
+ aaa:	bb 27       	eor	r27, r27
+ aac:	fa a2       	std	Y+34, r15	; 0x22
+ aae:	eb a2       	std	Y+35, r14	; 0x23
+ ab0:	8a 2f       	mov	r24, r26
+ ab2:	8f 70       	andi	r24, 0x0F	; 15
+ ab4:	89 a3       	std	Y+33, r24	; 0x21
+ ab6:	bc 8e       	std	Y+28, r11	; 0x1c
+ ab8:	ad 8e       	std	Y+29, r10	; 0x1d
+ aba:	08 e0       	ldi	r16, 0x08	; 8
+ abc:	10 e0       	ldi	r17, 0x00	; 0
+ abe:	20 e0       	ldi	r18, 0x00	; 0
+ ac0:	30 e0       	ldi	r19, 0x00	; 0
+ ac2:	ae 01       	movw	r20, r28
+ ac4:	44 5e       	subi	r20, 0xE4	; 228
+ ac6:	5f 4f       	sbci	r21, 0xFF	; 255
+ ac8:	62 e2       	ldi	r22, 0x22	; 34
+ aca:	ce 01       	movw	r24, r28
+ acc:	83 de       	rcall	.-762    	; 0x7d4 <writeRegister>
+ ace:	41 e0       	ldi	r20, 0x01	; 1
+ ad0:	61 e0       	ldi	r22, 0x01	; 1
+ ad2:	ce 01       	movw	r24, r28
+ ad4:	8b df       	rcall	.-234    	; 0x9ec <cm_resetPLLs>
+ ad6:	80 e0       	ldi	r24, 0x00	; 0
+ ad8:	90 e0       	ldi	r25, 0x00	; 0
+ ada:	df 91       	pop	r29
+ adc:	cf 91       	pop	r28
+ ade:	1f 91       	pop	r17
+ ae0:	0f 91       	pop	r16
+ ae2:	ff 90       	pop	r15
+ ae4:	ef 90       	pop	r14
+ ae6:	df 90       	pop	r13
+ ae8:	cf 90       	pop	r12
+ aea:	bf 90       	pop	r11
+ aec:	af 90       	pop	r10
+ aee:	08 95       	ret
+
+00000af0 <cm_si5351_init>:
+
+int cm_si5351_init(si5351_driver *inst, void *i2c_transfer_inst, setGet_I2C_Event_fpt i2c_transfer_evt){
+ af0:	ef 92       	push	r14
+ af2:	ff 92       	push	r15
+ af4:	0f 93       	push	r16
+ af6:	1f 93       	push	r17
+ af8:	cf 93       	push	r28
+ afa:	df 93       	push	r29
+ afc:	1f 92       	push	r1
+ afe:	cd b7       	in	r28, 0x3d	; 61
+ b00:	de b7       	in	r29, 0x3e	; 62
+
+	if(inst == NULL)return -1;
+ b02:	00 97       	sbiw	r24, 0x00	; 0
+ b04:	09 f4       	brne	.+2      	; 0xb08 <cm_si5351_init+0x18>
+ b06:	85 c0       	rjmp	.+266    	; 0xc12 <cm_si5351_init+0x122>
+	if(i2c_transfer_inst == NULL)return -1;
+ b08:	61 15       	cp	r22, r1
+ b0a:	71 05       	cpc	r23, r1
+ b0c:	09 f4       	brne	.+2      	; 0xb10 <cm_si5351_init+0x20>
+ b0e:	84 c0       	rjmp	.+264    	; 0xc18 <cm_si5351_init+0x128>
+	if(i2c_transfer_evt == NULL)return -1;
+ b10:	41 15       	cp	r20, r1
+ b12:	51 05       	cpc	r21, r1
+ b14:	09 f4       	brne	.+2      	; 0xb18 <cm_si5351_init+0x28>
+ b16:	83 c0       	rjmp	.+262    	; 0xc1e <cm_si5351_init+0x12e>
+ b18:	7c 01       	movw	r14, r24
+
+	inst->i2c_transfer_inst = i2c_transfer_inst;
+ b1a:	dc 01       	movw	r26, r24
+ b1c:	6d 93       	st	X+, r22
+ b1e:	7c 93       	st	X, r23
+ b20:	11 97       	sbiw	r26, 0x01	; 1
+	inst->i2c_transfer_evt = i2c_transfer_evt;
+ b22:	12 96       	adiw	r26, 0x02	; 2
+ b24:	4d 93       	st	X+, r20
+ b26:	5c 93       	st	X, r21
+ b28:	13 97       	sbiw	r26, 0x03	; 3
+
+	int ret = 0;
+
+	memset(&(inst->device_data),0x00,sizeof(si5351_data));
+ b2a:	fc 01       	movw	r30, r24
+ b2c:	34 96       	adiw	r30, 0x04	; 4
+ b2e:	84 e5       	ldi	r24, 0x54	; 84
+ b30:	df 01       	movw	r26, r30
+ b32:	1d 92       	st	X+, r1
+ b34:	8a 95       	dec	r24
+ b36:	e9 f7       	brne	.-6      	; 0xb32 <cm_si5351_init+0x42>
+
+	/* Disable all outputs setting CLKx_DIS high */
+	uint8_t temp = 0xff;
+ b38:	8f ef       	ldi	r24, 0xFF	; 255
+ b3a:	89 83       	std	Y+1, r24	; 0x01
+	writeRegister(inst,SI5351_REG_OUTPUT_ENABLE_CONTROL,&temp,1);
+ b3c:	01 e0       	ldi	r16, 0x01	; 1
+ b3e:	10 e0       	ldi	r17, 0x00	; 0
+ b40:	20 e0       	ldi	r18, 0x00	; 0
+ b42:	30 e0       	ldi	r19, 0x00	; 0
+ b44:	ae 01       	movw	r20, r28
+ b46:	4f 5f       	subi	r20, 0xFF	; 255
+ b48:	5f 4f       	sbci	r21, 0xFF	; 255
+ b4a:	63 e0       	ldi	r22, 0x03	; 3
+ b4c:	c7 01       	movw	r24, r14
+ b4e:	42 de       	rcall	.-892    	; 0x7d4 <writeRegister>
+
+	/* Power down all output drivers */
+	temp = 0x80;
+ b50:	80 e8       	ldi	r24, 0x80	; 128
+ b52:	89 83       	std	Y+1, r24	; 0x01
+	writeRegister(inst,SI5351_REG_CLK_0_CONTROL,&temp,1);
+ b54:	01 e0       	ldi	r16, 0x01	; 1
+ b56:	10 e0       	ldi	r17, 0x00	; 0
+ b58:	20 e0       	ldi	r18, 0x00	; 0
+ b5a:	30 e0       	ldi	r19, 0x00	; 0
+ b5c:	ae 01       	movw	r20, r28
+ b5e:	4f 5f       	subi	r20, 0xFF	; 255
+ b60:	5f 4f       	sbci	r21, 0xFF	; 255
+ b62:	60 e1       	ldi	r22, 0x10	; 16
+ b64:	c7 01       	movw	r24, r14
+ b66:	36 de       	rcall	.-916    	; 0x7d4 <writeRegister>
+	writeRegister(inst,SI5351_REG_CLK_1_CONTROL,&temp,1);
+ b68:	01 e0       	ldi	r16, 0x01	; 1
+ b6a:	10 e0       	ldi	r17, 0x00	; 0
+ b6c:	20 e0       	ldi	r18, 0x00	; 0
+ b6e:	30 e0       	ldi	r19, 0x00	; 0
+ b70:	ae 01       	movw	r20, r28
+ b72:	4f 5f       	subi	r20, 0xFF	; 255
+ b74:	5f 4f       	sbci	r21, 0xFF	; 255
+ b76:	61 e1       	ldi	r22, 0x11	; 17
+ b78:	c7 01       	movw	r24, r14
+ b7a:	2c de       	rcall	.-936    	; 0x7d4 <writeRegister>
+	writeRegister(inst,SI5351_REG_CLK_2_CONTROL,&temp,1);
+ b7c:	01 e0       	ldi	r16, 0x01	; 1
+ b7e:	10 e0       	ldi	r17, 0x00	; 0
+ b80:	20 e0       	ldi	r18, 0x00	; 0
+ b82:	30 e0       	ldi	r19, 0x00	; 0
+ b84:	ae 01       	movw	r20, r28
+ b86:	4f 5f       	subi	r20, 0xFF	; 255
+ b88:	5f 4f       	sbci	r21, 0xFF	; 255
+ b8a:	62 e1       	ldi	r22, 0x12	; 18
+ b8c:	c7 01       	movw	r24, r14
+ b8e:	22 de       	rcall	.-956    	; 0x7d4 <writeRegister>
+	writeRegister(inst,SI5351_REG_CLK_3_CONTROL,&temp,1);
+ b90:	01 e0       	ldi	r16, 0x01	; 1
+ b92:	10 e0       	ldi	r17, 0x00	; 0
+ b94:	20 e0       	ldi	r18, 0x00	; 0
+ b96:	30 e0       	ldi	r19, 0x00	; 0
+ b98:	ae 01       	movw	r20, r28
+ b9a:	4f 5f       	subi	r20, 0xFF	; 255
+ b9c:	5f 4f       	sbci	r21, 0xFF	; 255
+ b9e:	63 e1       	ldi	r22, 0x13	; 19
+ ba0:	c7 01       	movw	r24, r14
+ ba2:	18 de       	rcall	.-976    	; 0x7d4 <writeRegister>
+	writeRegister(inst,SI5351_REG_CLK_4_CONTROL,&temp,1);
+ ba4:	01 e0       	ldi	r16, 0x01	; 1
+ ba6:	10 e0       	ldi	r17, 0x00	; 0
+ ba8:	20 e0       	ldi	r18, 0x00	; 0
+ baa:	30 e0       	ldi	r19, 0x00	; 0
+ bac:	ae 01       	movw	r20, r28
+ bae:	4f 5f       	subi	r20, 0xFF	; 255
+ bb0:	5f 4f       	sbci	r21, 0xFF	; 255
+ bb2:	64 e1       	ldi	r22, 0x14	; 20
+ bb4:	c7 01       	movw	r24, r14
+ bb6:	0e de       	rcall	.-996    	; 0x7d4 <writeRegister>
+	writeRegister(inst,SI5351_REG_CLK_5_CONTROL,&temp,1);
+ bb8:	01 e0       	ldi	r16, 0x01	; 1
+ bba:	10 e0       	ldi	r17, 0x00	; 0
+ bbc:	20 e0       	ldi	r18, 0x00	; 0
+ bbe:	30 e0       	ldi	r19, 0x00	; 0
+ bc0:	ae 01       	movw	r20, r28
+ bc2:	4f 5f       	subi	r20, 0xFF	; 255
+ bc4:	5f 4f       	sbci	r21, 0xFF	; 255
+ bc6:	65 e1       	ldi	r22, 0x15	; 21
+ bc8:	c7 01       	movw	r24, r14
+ bca:	04 de       	rcall	.-1016   	; 0x7d4 <writeRegister>
+	writeRegister(inst,SI5351_REG_CLK_6_CONTROL,&temp,1);
+ bcc:	01 e0       	ldi	r16, 0x01	; 1
+ bce:	10 e0       	ldi	r17, 0x00	; 0
+ bd0:	20 e0       	ldi	r18, 0x00	; 0
+ bd2:	30 e0       	ldi	r19, 0x00	; 0
+ bd4:	ae 01       	movw	r20, r28
+ bd6:	4f 5f       	subi	r20, 0xFF	; 255
+ bd8:	5f 4f       	sbci	r21, 0xFF	; 255
+ bda:	66 e1       	ldi	r22, 0x16	; 22
+ bdc:	c7 01       	movw	r24, r14
+ bde:	fa dd       	rcall	.-1036   	; 0x7d4 <writeRegister>
+	writeRegister(inst,SI5351_REG_CLK_7_CONTROL,&temp,1);
+ be0:	01 e0       	ldi	r16, 0x01	; 1
+ be2:	10 e0       	ldi	r17, 0x00	; 0
+ be4:	20 e0       	ldi	r18, 0x00	; 0
+ be6:	30 e0       	ldi	r19, 0x00	; 0
+ be8:	ae 01       	movw	r20, r28
+ bea:	4f 5f       	subi	r20, 0xFF	; 255
+ bec:	5f 4f       	sbci	r21, 0xFF	; 255
+ bee:	67 e1       	ldi	r22, 0x17	; 23
+ bf0:	c7 01       	movw	r24, r14
+ bf2:	f0 dd       	rcall	.-1056   	; 0x7d4 <writeRegister>
+
+	temp = SI5351_CRYSTAL_LOAD_10PF;
+ bf4:	80 ec       	ldi	r24, 0xC0	; 192
+ bf6:	89 83       	std	Y+1, r24	; 0x01
+
+	writeRegister(inst,SI5351_REG_CRYSTAL_LOAD_CAPACITANCE,&temp,1);
+ bf8:	01 e0       	ldi	r16, 0x01	; 1
+ bfa:	10 e0       	ldi	r17, 0x00	; 0
+ bfc:	20 e0       	ldi	r18, 0x00	; 0
+ bfe:	30 e0       	ldi	r19, 0x00	; 0
+ c00:	ae 01       	movw	r20, r28
+ c02:	4f 5f       	subi	r20, 0xFF	; 255
+ c04:	5f 4f       	sbci	r21, 0xFF	; 255
+ c06:	67 eb       	ldi	r22, 0xB7	; 183
+ c08:	c7 01       	movw	r24, r14
+ c0a:	e4 dd       	rcall	.-1080   	; 0x7d4 <writeRegister>
+	return ret;
+ c0c:	80 e0       	ldi	r24, 0x00	; 0
+ c0e:	90 e0       	ldi	r25, 0x00	; 0
+ c10:	08 c0       	rjmp	.+16     	; 0xc22 <cm_si5351_init+0x132>
+	return inst->device_data.deviceStatus.REVID;
+}
+
+int cm_si5351_init(si5351_driver *inst, void *i2c_transfer_inst, setGet_I2C_Event_fpt i2c_transfer_evt){
+
+	if(inst == NULL)return -1;
+ c12:	8f ef       	ldi	r24, 0xFF	; 255
+ c14:	9f ef       	ldi	r25, 0xFF	; 255
+ c16:	05 c0       	rjmp	.+10     	; 0xc22 <cm_si5351_init+0x132>
+	if(i2c_transfer_inst == NULL)return -1;
+ c18:	8f ef       	ldi	r24, 0xFF	; 255
+ c1a:	9f ef       	ldi	r25, 0xFF	; 255
+ c1c:	02 c0       	rjmp	.+4      	; 0xc22 <cm_si5351_init+0x132>
+	if(i2c_transfer_evt == NULL)return -1;
+ c1e:	8f ef       	ldi	r24, 0xFF	; 255
+ c20:	9f ef       	ldi	r25, 0xFF	; 255
+	writeRegister(inst,SI5351_REG_CRYSTAL_LOAD_CAPACITANCE,&temp,1);
+	return ret;
+
+
+
+}
+ c22:	0f 90       	pop	r0
+ c24:	df 91       	pop	r29
+ c26:	cf 91       	pop	r28
+ c28:	1f 91       	pop	r17
+ c2a:	0f 91       	pop	r16
+ c2c:	ff 90       	pop	r15
+ c2e:	ef 90       	pop	r14
+ c30:	08 95       	ret
+
+00000c32 <malloc>:
+ c32:	0f 93       	push	r16
+ c34:	1f 93       	push	r17
+ c36:	cf 93       	push	r28
+ c38:	df 93       	push	r29
+ c3a:	82 30       	cpi	r24, 0x02	; 2
+ c3c:	91 05       	cpc	r25, r1
+ c3e:	10 f4       	brcc	.+4      	; 0xc44 <malloc+0x12>
+ c40:	82 e0       	ldi	r24, 0x02	; 2
+ c42:	90 e0       	ldi	r25, 0x00	; 0
+ c44:	e0 91 69 3f 	lds	r30, 0x3F69	; 0x803f69 <__flp>
+ c48:	f0 91 6a 3f 	lds	r31, 0x3F6A	; 0x803f6a <__flp+0x1>
+ c4c:	20 e0       	ldi	r18, 0x00	; 0
+ c4e:	30 e0       	ldi	r19, 0x00	; 0
+ c50:	a0 e0       	ldi	r26, 0x00	; 0
+ c52:	b0 e0       	ldi	r27, 0x00	; 0
+ c54:	30 97       	sbiw	r30, 0x00	; 0
+ c56:	19 f1       	breq	.+70     	; 0xc9e <malloc+0x6c>
+ c58:	40 81       	ld	r20, Z
+ c5a:	51 81       	ldd	r21, Z+1	; 0x01
+ c5c:	02 81       	ldd	r16, Z+2	; 0x02
+ c5e:	13 81       	ldd	r17, Z+3	; 0x03
+ c60:	48 17       	cp	r20, r24
+ c62:	59 07       	cpc	r21, r25
+ c64:	c8 f0       	brcs	.+50     	; 0xc98 <malloc+0x66>
+ c66:	84 17       	cp	r24, r20
+ c68:	95 07       	cpc	r25, r21
+ c6a:	69 f4       	brne	.+26     	; 0xc86 <malloc+0x54>
+ c6c:	10 97       	sbiw	r26, 0x00	; 0
+ c6e:	31 f0       	breq	.+12     	; 0xc7c <malloc+0x4a>
+ c70:	12 96       	adiw	r26, 0x02	; 2
+ c72:	0c 93       	st	X, r16
+ c74:	12 97       	sbiw	r26, 0x02	; 2
+ c76:	13 96       	adiw	r26, 0x03	; 3
+ c78:	1c 93       	st	X, r17
+ c7a:	27 c0       	rjmp	.+78     	; 0xcca <malloc+0x98>
+ c7c:	00 93 69 3f 	sts	0x3F69, r16	; 0x803f69 <__flp>
+ c80:	10 93 6a 3f 	sts	0x3F6A, r17	; 0x803f6a <__flp+0x1>
+ c84:	22 c0       	rjmp	.+68     	; 0xcca <malloc+0x98>
+ c86:	21 15       	cp	r18, r1
+ c88:	31 05       	cpc	r19, r1
+ c8a:	19 f0       	breq	.+6      	; 0xc92 <malloc+0x60>
+ c8c:	42 17       	cp	r20, r18
+ c8e:	53 07       	cpc	r21, r19
+ c90:	18 f4       	brcc	.+6      	; 0xc98 <malloc+0x66>
+ c92:	9a 01       	movw	r18, r20
+ c94:	bd 01       	movw	r22, r26
+ c96:	ef 01       	movw	r28, r30
+ c98:	df 01       	movw	r26, r30
+ c9a:	f8 01       	movw	r30, r16
+ c9c:	db cf       	rjmp	.-74     	; 0xc54 <malloc+0x22>
+ c9e:	21 15       	cp	r18, r1
+ ca0:	31 05       	cpc	r19, r1
+ ca2:	f9 f0       	breq	.+62     	; 0xce2 <malloc+0xb0>
+ ca4:	28 1b       	sub	r18, r24
+ ca6:	39 0b       	sbc	r19, r25
+ ca8:	24 30       	cpi	r18, 0x04	; 4
+ caa:	31 05       	cpc	r19, r1
+ cac:	80 f4       	brcc	.+32     	; 0xcce <malloc+0x9c>
+ cae:	8a 81       	ldd	r24, Y+2	; 0x02
+ cb0:	9b 81       	ldd	r25, Y+3	; 0x03
+ cb2:	61 15       	cp	r22, r1
+ cb4:	71 05       	cpc	r23, r1
+ cb6:	21 f0       	breq	.+8      	; 0xcc0 <malloc+0x8e>
+ cb8:	fb 01       	movw	r30, r22
+ cba:	82 83       	std	Z+2, r24	; 0x02
+ cbc:	93 83       	std	Z+3, r25	; 0x03
+ cbe:	04 c0       	rjmp	.+8      	; 0xcc8 <malloc+0x96>
+ cc0:	80 93 69 3f 	sts	0x3F69, r24	; 0x803f69 <__flp>
+ cc4:	90 93 6a 3f 	sts	0x3F6A, r25	; 0x803f6a <__flp+0x1>
+ cc8:	fe 01       	movw	r30, r28
+ cca:	32 96       	adiw	r30, 0x02	; 2
+ ccc:	44 c0       	rjmp	.+136    	; 0xd56 <malloc+0x124>
+ cce:	fe 01       	movw	r30, r28
+ cd0:	e2 0f       	add	r30, r18
+ cd2:	f3 1f       	adc	r31, r19
+ cd4:	81 93       	st	Z+, r24
+ cd6:	91 93       	st	Z+, r25
+ cd8:	22 50       	subi	r18, 0x02	; 2
+ cda:	31 09       	sbc	r19, r1
+ cdc:	28 83       	st	Y, r18
+ cde:	39 83       	std	Y+1, r19	; 0x01
+ ce0:	3a c0       	rjmp	.+116    	; 0xd56 <malloc+0x124>
+ ce2:	20 91 67 3f 	lds	r18, 0x3F67	; 0x803f67 <__brkval>
+ ce6:	30 91 68 3f 	lds	r19, 0x3F68	; 0x803f68 <__brkval+0x1>
+ cea:	23 2b       	or	r18, r19
+ cec:	41 f4       	brne	.+16     	; 0xcfe <malloc+0xcc>
+ cee:	20 91 02 3f 	lds	r18, 0x3F02	; 0x803f02 <__malloc_heap_start>
+ cf2:	30 91 03 3f 	lds	r19, 0x3F03	; 0x803f03 <__malloc_heap_start+0x1>
+ cf6:	20 93 67 3f 	sts	0x3F67, r18	; 0x803f67 <__brkval>
+ cfa:	30 93 68 3f 	sts	0x3F68, r19	; 0x803f68 <__brkval+0x1>
+ cfe:	20 91 00 3f 	lds	r18, 0x3F00	; 0x803f00 <__DATA_REGION_ORIGIN__>
+ d02:	30 91 01 3f 	lds	r19, 0x3F01	; 0x803f01 <__DATA_REGION_ORIGIN__+0x1>
+ d06:	21 15       	cp	r18, r1
+ d08:	31 05       	cpc	r19, r1
+ d0a:	41 f4       	brne	.+16     	; 0xd1c <malloc+0xea>
+ d0c:	2d b7       	in	r18, 0x3d	; 61
+ d0e:	3e b7       	in	r19, 0x3e	; 62
+ d10:	40 91 04 3f 	lds	r20, 0x3F04	; 0x803f04 <__malloc_margin>
+ d14:	50 91 05 3f 	lds	r21, 0x3F05	; 0x803f05 <__malloc_margin+0x1>
+ d18:	24 1b       	sub	r18, r20
+ d1a:	35 0b       	sbc	r19, r21
+ d1c:	e0 91 67 3f 	lds	r30, 0x3F67	; 0x803f67 <__brkval>
+ d20:	f0 91 68 3f 	lds	r31, 0x3F68	; 0x803f68 <__brkval+0x1>
+ d24:	e2 17       	cp	r30, r18
+ d26:	f3 07       	cpc	r31, r19
+ d28:	a0 f4       	brcc	.+40     	; 0xd52 <malloc+0x120>
+ d2a:	2e 1b       	sub	r18, r30
+ d2c:	3f 0b       	sbc	r19, r31
+ d2e:	28 17       	cp	r18, r24
+ d30:	39 07       	cpc	r19, r25
+ d32:	78 f0       	brcs	.+30     	; 0xd52 <malloc+0x120>
+ d34:	ac 01       	movw	r20, r24
+ d36:	4e 5f       	subi	r20, 0xFE	; 254
+ d38:	5f 4f       	sbci	r21, 0xFF	; 255
+ d3a:	24 17       	cp	r18, r20
+ d3c:	35 07       	cpc	r19, r21
+ d3e:	48 f0       	brcs	.+18     	; 0xd52 <malloc+0x120>
+ d40:	4e 0f       	add	r20, r30
+ d42:	5f 1f       	adc	r21, r31
+ d44:	40 93 67 3f 	sts	0x3F67, r20	; 0x803f67 <__brkval>
+ d48:	50 93 68 3f 	sts	0x3F68, r21	; 0x803f68 <__brkval+0x1>
+ d4c:	81 93       	st	Z+, r24
+ d4e:	91 93       	st	Z+, r25
+ d50:	02 c0       	rjmp	.+4      	; 0xd56 <malloc+0x124>
+ d52:	e0 e0       	ldi	r30, 0x00	; 0
+ d54:	f0 e0       	ldi	r31, 0x00	; 0
+ d56:	cf 01       	movw	r24, r30
+ d58:	df 91       	pop	r29
+ d5a:	cf 91       	pop	r28
+ d5c:	1f 91       	pop	r17
+ d5e:	0f 91       	pop	r16
+ d60:	08 95       	ret
+
+00000d62 <free>:
+ d62:	cf 93       	push	r28
+ d64:	df 93       	push	r29
+ d66:	00 97       	sbiw	r24, 0x00	; 0
+ d68:	09 f4       	brne	.+2      	; 0xd6c <free+0xa>
+ d6a:	81 c0       	rjmp	.+258    	; 0xe6e <free+0x10c>
+ d6c:	fc 01       	movw	r30, r24
+ d6e:	32 97       	sbiw	r30, 0x02	; 2
+ d70:	12 82       	std	Z+2, r1	; 0x02
+ d72:	13 82       	std	Z+3, r1	; 0x03
+ d74:	a0 91 69 3f 	lds	r26, 0x3F69	; 0x803f69 <__flp>
+ d78:	b0 91 6a 3f 	lds	r27, 0x3F6A	; 0x803f6a <__flp+0x1>
+ d7c:	10 97       	sbiw	r26, 0x00	; 0
+ d7e:	81 f4       	brne	.+32     	; 0xda0 <free+0x3e>
+ d80:	20 81       	ld	r18, Z
+ d82:	31 81       	ldd	r19, Z+1	; 0x01
+ d84:	82 0f       	add	r24, r18
+ d86:	93 1f       	adc	r25, r19
+ d88:	20 91 67 3f 	lds	r18, 0x3F67	; 0x803f67 <__brkval>
+ d8c:	30 91 68 3f 	lds	r19, 0x3F68	; 0x803f68 <__brkval+0x1>
+ d90:	28 17       	cp	r18, r24
+ d92:	39 07       	cpc	r19, r25
+ d94:	51 f5       	brne	.+84     	; 0xdea <free+0x88>
+ d96:	e0 93 67 3f 	sts	0x3F67, r30	; 0x803f67 <__brkval>
+ d9a:	f0 93 68 3f 	sts	0x3F68, r31	; 0x803f68 <__brkval+0x1>
+ d9e:	67 c0       	rjmp	.+206    	; 0xe6e <free+0x10c>
+ da0:	ed 01       	movw	r28, r26
+ da2:	20 e0       	ldi	r18, 0x00	; 0
+ da4:	30 e0       	ldi	r19, 0x00	; 0
+ da6:	ce 17       	cp	r28, r30
+ da8:	df 07       	cpc	r29, r31
+ daa:	40 f4       	brcc	.+16     	; 0xdbc <free+0x5a>
+ dac:	4a 81       	ldd	r20, Y+2	; 0x02
+ dae:	5b 81       	ldd	r21, Y+3	; 0x03
+ db0:	9e 01       	movw	r18, r28
+ db2:	41 15       	cp	r20, r1
+ db4:	51 05       	cpc	r21, r1
+ db6:	f1 f0       	breq	.+60     	; 0xdf4 <free+0x92>
+ db8:	ea 01       	movw	r28, r20
+ dba:	f5 cf       	rjmp	.-22     	; 0xda6 <free+0x44>
+ dbc:	c2 83       	std	Z+2, r28	; 0x02
+ dbe:	d3 83       	std	Z+3, r29	; 0x03
+ dc0:	40 81       	ld	r20, Z
+ dc2:	51 81       	ldd	r21, Z+1	; 0x01
+ dc4:	84 0f       	add	r24, r20
+ dc6:	95 1f       	adc	r25, r21
+ dc8:	c8 17       	cp	r28, r24
+ dca:	d9 07       	cpc	r29, r25
+ dcc:	59 f4       	brne	.+22     	; 0xde4 <free+0x82>
+ dce:	88 81       	ld	r24, Y
+ dd0:	99 81       	ldd	r25, Y+1	; 0x01
+ dd2:	84 0f       	add	r24, r20
+ dd4:	95 1f       	adc	r25, r21
+ dd6:	02 96       	adiw	r24, 0x02	; 2
+ dd8:	80 83       	st	Z, r24
+ dda:	91 83       	std	Z+1, r25	; 0x01
+ ddc:	8a 81       	ldd	r24, Y+2	; 0x02
+ dde:	9b 81       	ldd	r25, Y+3	; 0x03
+ de0:	82 83       	std	Z+2, r24	; 0x02
+ de2:	93 83       	std	Z+3, r25	; 0x03
+ de4:	21 15       	cp	r18, r1
+ de6:	31 05       	cpc	r19, r1
+ de8:	29 f4       	brne	.+10     	; 0xdf4 <free+0x92>
+ dea:	e0 93 69 3f 	sts	0x3F69, r30	; 0x803f69 <__flp>
+ dee:	f0 93 6a 3f 	sts	0x3F6A, r31	; 0x803f6a <__flp+0x1>
+ df2:	3d c0       	rjmp	.+122    	; 0xe6e <free+0x10c>
+ df4:	e9 01       	movw	r28, r18
+ df6:	ea 83       	std	Y+2, r30	; 0x02
+ df8:	fb 83       	std	Y+3, r31	; 0x03
+ dfa:	49 91       	ld	r20, Y+
+ dfc:	59 91       	ld	r21, Y+
+ dfe:	c4 0f       	add	r28, r20
+ e00:	d5 1f       	adc	r29, r21
+ e02:	ec 17       	cp	r30, r28
+ e04:	fd 07       	cpc	r31, r29
+ e06:	61 f4       	brne	.+24     	; 0xe20 <free+0xbe>
+ e08:	80 81       	ld	r24, Z
+ e0a:	91 81       	ldd	r25, Z+1	; 0x01
+ e0c:	84 0f       	add	r24, r20
+ e0e:	95 1f       	adc	r25, r21
+ e10:	02 96       	adiw	r24, 0x02	; 2
+ e12:	e9 01       	movw	r28, r18
+ e14:	88 83       	st	Y, r24
+ e16:	99 83       	std	Y+1, r25	; 0x01
+ e18:	82 81       	ldd	r24, Z+2	; 0x02
+ e1a:	93 81       	ldd	r25, Z+3	; 0x03
+ e1c:	8a 83       	std	Y+2, r24	; 0x02
+ e1e:	9b 83       	std	Y+3, r25	; 0x03
+ e20:	e0 e0       	ldi	r30, 0x00	; 0
+ e22:	f0 e0       	ldi	r31, 0x00	; 0
+ e24:	12 96       	adiw	r26, 0x02	; 2
+ e26:	8d 91       	ld	r24, X+
+ e28:	9c 91       	ld	r25, X
+ e2a:	13 97       	sbiw	r26, 0x03	; 3
+ e2c:	00 97       	sbiw	r24, 0x00	; 0
+ e2e:	19 f0       	breq	.+6      	; 0xe36 <free+0xd4>
+ e30:	fd 01       	movw	r30, r26
+ e32:	dc 01       	movw	r26, r24
+ e34:	f7 cf       	rjmp	.-18     	; 0xe24 <free+0xc2>
+ e36:	8d 91       	ld	r24, X+
+ e38:	9c 91       	ld	r25, X
+ e3a:	11 97       	sbiw	r26, 0x01	; 1
+ e3c:	9d 01       	movw	r18, r26
+ e3e:	2e 5f       	subi	r18, 0xFE	; 254
+ e40:	3f 4f       	sbci	r19, 0xFF	; 255
+ e42:	82 0f       	add	r24, r18
+ e44:	93 1f       	adc	r25, r19
+ e46:	20 91 67 3f 	lds	r18, 0x3F67	; 0x803f67 <__brkval>
+ e4a:	30 91 68 3f 	lds	r19, 0x3F68	; 0x803f68 <__brkval+0x1>
+ e4e:	28 17       	cp	r18, r24
+ e50:	39 07       	cpc	r19, r25
+ e52:	69 f4       	brne	.+26     	; 0xe6e <free+0x10c>
+ e54:	30 97       	sbiw	r30, 0x00	; 0
+ e56:	29 f4       	brne	.+10     	; 0xe62 <free+0x100>
+ e58:	10 92 69 3f 	sts	0x3F69, r1	; 0x803f69 <__flp>
+ e5c:	10 92 6a 3f 	sts	0x3F6A, r1	; 0x803f6a <__flp+0x1>
+ e60:	02 c0       	rjmp	.+4      	; 0xe66 <free+0x104>
+ e62:	12 82       	std	Z+2, r1	; 0x02
+ e64:	13 82       	std	Z+3, r1	; 0x03
+ e66:	a0 93 67 3f 	sts	0x3F67, r26	; 0x803f67 <__brkval>
+ e6a:	b0 93 68 3f 	sts	0x3F68, r27	; 0x803f68 <__brkval+0x1>
+ e6e:	df 91       	pop	r29
+ e70:	cf 91       	pop	r28
+ e72:	08 95       	ret
+
+00000e74 <memcpy>:
+ e74:	fb 01       	movw	r30, r22
+ e76:	dc 01       	movw	r26, r24
+ e78:	02 c0       	rjmp	.+4      	; 0xe7e <memcpy+0xa>
+ e7a:	01 90       	ld	r0, Z+
+ e7c:	0d 92       	st	X+, r0
+ e7e:	41 50       	subi	r20, 0x01	; 1
+ e80:	50 40       	sbci	r21, 0x00	; 0
+ e82:	d8 f7       	brcc	.-10     	; 0xe7a <memcpy+0x6>
+ e84:	08 95       	ret
+
+00000e86 <eeprom_read_byte>:
+ e86:	03 d0       	rcall	.+6      	; 0xe8e <eeprom_mapen>
+ e88:	80 81       	ld	r24, Z
+ e8a:	99 27       	eor	r25, r25
+ e8c:	08 95       	ret
+
+00000e8e <eeprom_mapen>:
+ e8e:	fc 01       	movw	r30, r24
+ e90:	e0 50       	subi	r30, 0x00	; 0
+ e92:	fc 4e       	sbci	r31, 0xEC	; 236
+ e94:	08 95       	ret
+
+00000e96 <eeprom_write_byte>:
+ e96:	26 2f       	mov	r18, r22
+
+00000e98 <eeprom_write_r18>:
+ e98:	af 93       	push	r26
+ e9a:	bf 93       	push	r27
+ e9c:	e0 e0       	ldi	r30, 0x00	; 0
+ e9e:	f0 e1       	ldi	r31, 0x10	; 16
+ ea0:	32 81       	ldd	r19, Z+2	; 0x02
+ ea2:	31 fd       	sbrc	r19, 1
+ ea4:	fd cf       	rjmp	.-6      	; 0xea0 <eeprom_write_r18+0x8>
+ ea6:	dc 01       	movw	r26, r24
+ ea8:	a0 50       	subi	r26, 0x00	; 0
+ eaa:	bc 4e       	sbci	r27, 0xEC	; 236
+ eac:	2c 93       	st	X, r18
+ eae:	2d e9       	ldi	r18, 0x9D	; 157
+ eb0:	24 bf       	out	0x34, r18	; 52
+ eb2:	23 e0       	ldi	r18, 0x03	; 3
+ eb4:	20 83       	st	Z, r18
+ eb6:	01 96       	adiw	r24, 0x01	; 1
+ eb8:	bf 91       	pop	r27
+ eba:	af 91       	pop	r26
+ ebc:	08 95       	ret
+
+00000ebe <_exit>:
+ ebe:	f8 94       	cli
+
+00000ec0 <__stop_program>:
+ ec0:	ff cf       	rjmp	.-2      	; 0xec0 <__stop_program>
diff --git a/storno_cqp6xx_digital_xtal/Debug/storno_cqp6xx_digital_xtal.map b/storno_cqp6xx_digital_xtal/Debug/storno_cqp6xx_digital_xtal.map
index e7edfb6..4d67400 100644
--- a/storno_cqp6xx_digital_xtal/Debug/storno_cqp6xx_digital_xtal.map
+++ b/storno_cqp6xx_digital_xtal/Debug/storno_cqp6xx_digital_xtal.map
@@ -43,7 +43,7 @@ c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/..
 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/avrxmega3/short-calls\libgcc.a(_exit.o)
                               C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls/crtattiny402.o (exit)
 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/avrxmega3/short-calls\libgcc.a(_copy_data.o)
-                              main.o (__do_copy_data)
+                              cqm6xx_app.o (__do_copy_data)
 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/avrxmega3/short-calls\libgcc.a(_clear_bss.o)
                               avr_uart_driver/avr_uart.o (__do_clear_bss)
 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/../../../../avr/lib/avrxmega3/short-calls\libc.a(malloc.o)
@@ -58,6 +58,7 @@ C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/
 Allocating common symbols
 Common symbol       size              file
 
+temp_msg            0x19              cqm6xx_app.o
 storno_xtal_app     0x6               main.o
 __brkval            0x2               c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/../../../../avr/lib/avrxmega3/short-calls\libc.a(malloc.o)
 __flp               0x2               c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/../../../../avr/lib/avrxmega3/short-calls\libc.a(malloc.o)
@@ -74,58 +75,18 @@ Discarded input sections
  .bss           0x00000000        0x0 avr_gpio_driver/avr_gpio.o
  .text.gpio_set_level
                 0x00000000       0x34 avr_gpio_driver/avr_gpio.o
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                 0x00000000       0x34 avr_gpio_driver/avr_gpio.o
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  .text.i2c_byte_write
                 0x00000000       0x48 avr_i2c_driver/avr_i2c.o
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                 0x00000000       0x34 avr_i2c_driver/avr_i2c.o
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-                0x00000000       0x8c avr_i2c_driver/avr_i2c.o
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                 0x00000000        0xe avr_uart_driver/avr_uart.o
  .text.cm_uart_receive
@@ -135,101 +96,26 @@ Discarded input sections
  .text          0x00000000        0x0 cm_msg/cm_msg.o
  .data          0x00000000        0x0 cm_msg/cm_msg.o
  .bss           0x00000000        0x0 cm_msg/cm_msg.o
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-                0x00000000       0x9e cm_msg/cm_msg.o
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-                0x00000000        0x1 cm_msg/cm_msg.o
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- .bss.s_msg_cmplete_evt_fpt
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-                0x00000000        0xc cqm6xx_app.o
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-                0x00000000       0x76 cqm6xx_app.o
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-                0x00000000       0x56 cqm6xx_app.o
- .text.programPLL_Parameters
-                0x00000000        0x6 cqm6xx_app.o
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  .text          0x00000000        0x0 main.o
  .data          0x00000000        0x0 main.o
  .bss           0x00000000        0x0 main.o
- COMMON         0x00000000        0x6 main.o
+ .bss.data      0x00000000       0x19 main.o
+ .data.data_set
+                0x00000000       0x19 main.o
  .text          0x00000000        0x0 si5351_driver/si5351_driver.o
  .data          0x00000000        0x0 si5351_driver/si5351_driver.o
  .bss           0x00000000        0x0 si5351_driver/si5351_driver.o
  .text.readRegister
                 0x00000000       0x80 si5351_driver/si5351_driver.o
- .text.writeRegister
-                0x00000000       0x78 si5351_driver/si5351_driver.o
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-                0x00000000       0xcc si5351_driver/si5351_driver.o
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                 0x00000000      0x116 si5351_driver/si5351_driver.o
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-                0x00000000       0x40 si5351_driver/si5351_driver.o
- .text.cm_setCLKControl
-                0x00000000       0x5c si5351_driver/si5351_driver.o
- .text.cm_setInputSource
-                0x00000000       0x3e si5351_driver/si5351_driver.o
- .text.cm_resetPLLs
-                0x00000000       0x48 si5351_driver/si5351_driver.o
- .text.cm_setPllParamRaw
-                0x00000000       0xbc si5351_driver/si5351_driver.o
  .text.cm_setPLLParameters
                 0x00000000      0x2ce si5351_driver/si5351_driver.o
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                 0x00000000       0x2a si5351_driver/si5351_driver.o
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- .debug_info    0x00000000     0x16d1 si5351_driver/si5351_driver.o
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- .debug_ranges  0x00000000       0x68 si5351_driver/si5351_driver.o
- .debug_line    0x00000000      0x55f si5351_driver/si5351_driver.o
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- .comment       0x00000000       0x31 si5351_driver/si5351_driver.o
- .debug_frame   0x00000000      0x28c si5351_driver/si5351_driver.o
  .text          0x00000000        0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/../../../../avr/lib/avrxmega3/short-calls\libm.a(addsf3.o)
  .data          0x00000000        0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/../../../../avr/lib/avrxmega3/short-calls\libm.a(addsf3.o)
  .bss           0x00000000        0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/../../../../avr/lib/avrxmega3/short-calls\libm.a(addsf3.o)
@@ -390,17 +276,10 @@ Discarded input sections
  .text.libgcc.fixed
                 0x00000000        0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/avrxmega3/short-calls\libgcc.a(_clear_bss.o)
  .text          0x00000000        0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/../../../../avr/lib/avrxmega3/short-calls\libc.a(malloc.o)
- .data          0x00000000        0x6 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/../../../../avr/lib/avrxmega3/short-calls\libc.a(malloc.o)
  .bss           0x00000000        0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/../../../../avr/lib/avrxmega3/short-calls\libc.a(malloc.o)
- .text.avr-libc
-                0x00000000      0x242 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/../../../../avr/lib/avrxmega3/short-calls\libc.a(malloc.o)
- .comment       0x00000000       0x31 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/../../../../avr/lib/avrxmega3/short-calls\libc.a(malloc.o)
- COMMON         0x00000000        0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/../../../../avr/lib/avrxmega3/short-calls\libc.a(malloc.o)
  .text          0x00000000        0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/../../../../avr/lib/avrxmega3/short-calls\libc.a(memcpy.o)
  .data          0x00000000        0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/../../../../avr/lib/avrxmega3/short-calls\libc.a(memcpy.o)
  .bss           0x00000000        0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/../../../../avr/lib/avrxmega3/short-calls\libc.a(memcpy.o)
- .text.avr-libc
-                0x00000000       0x12 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/../../../../avr/lib/avrxmega3/short-calls\libc.a(memcpy.o)
  .text          0x00000000        0x0 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls\libattiny402.a(eerd_byte.o)
  .data          0x00000000        0x0 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls\libattiny402.a(eerd_byte.o)
  .bss           0x00000000        0x0 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls\libattiny402.a(eerd_byte.o)
@@ -543,7 +422,7 @@ END GROUP
 .rela.plt
  *(.rela.plt)
 
-.text           0x00000000      0x19c
+.text           0x00000000      0xec2
  *(.vectors)
  .vectors       0x00000000       0x34 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls/crtattiny402.o
                 0x00000000                __vector_default
@@ -630,29 +509,117 @@ END GROUP
                 0x0000006c                . = ALIGN (0x2)
  *(.text.*)
  .text.cm_EEPROM_write
-                0x0000006c       0x36 avr_eeprom_driver/avr_eeprom_driver.o
+                0x0000006c       0x3c avr_eeprom_driver/avr_eeprom_driver.o
                 0x0000006c                cm_EEPROM_write
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-                0x000000a2       0x10 avr_eeprom_driver/avr_eeprom_driver.o
-                0x000000a2                cm_EEPROM_read
+                0x000000a8       0x46 avr_eeprom_driver/avr_eeprom_driver.o
+                0x000000a8                cm_EEPROM_read
+ .text.gpio_get_level
+                0x000000ee       0x24 avr_gpio_driver/avr_gpio.o
+                0x000000ee                gpio_get_level
+ .text.i2c_reset
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+ .text.i2c_write_devAddr
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+                0x00000122                i2c_write_devAddr
+ .text.i2c_write
+                0x00000144       0x92 avr_i2c_driver/avr_i2c.o
+                0x00000144                i2c_write
+ .text.i2c_read
+                0x000001d6       0x8c avr_i2c_driver/avr_i2c.o
+                0x000001d6                i2c_read
+ .text.i2c_IsDeviceReady
+                0x00000262       0x2c avr_i2c_driver/avr_i2c.o
+                0x00000262                i2c_IsDeviceReady
+ .text.cm_i2c_init
+                0x0000028e       0x34 avr_i2c_driver/avr_i2c.o
+                0x0000028e                cm_i2c_init
+ .text.cm_i2c_addDev
+                0x000002c2       0x3c avr_i2c_driver/avr_i2c.o
+                0x000002c2                cm_i2c_addDev
+ .text.cm_i2c_transfer
+                0x000002fe       0x34 avr_i2c_driver/avr_i2c.o
+                0x000002fe                cm_i2c_transfer
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-                0x000000b2       0x56 avr_uart_driver/avr_uart.o
-                0x000000b2                __vector_22
- .text.main     0x00000108       0x58 main.o
-                0x00000108                main
+                0x00000332       0x56 avr_uart_driver/avr_uart.o
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+                0x00000388       0x60 avr_uart_driver/avr_uart.o
+                0x00000388                cm_uart_init
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+                0x000003e8       0x9e cm_msg/cm_msg.o
+                0x000003e8                cm_msgSync_Byte_DecodeSC
+ .text.cm_msg_DecodeMsg_Byte
+                0x00000486       0xa8 cm_msg/cm_msg.o
+                0x00000486                cm_msg_DecodeMsg_Byte
+ .text.cm_MsgCompleteEvt_Register
+                0x0000052e       0x1c cm_msg/cm_msg.o
+                0x0000052e                cm_MsgCompleteEvt_Register
+ .text.isStructValid
+                0x0000054a       0x1a cqm6xx_app.o
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+                0x00000564       0x96 cqm6xx_app.o
+ .text.cqm6xx_app_loadPLLParam
+                0x000005fa       0x52 cqm6xx_app.o
+ .text.cqm6xx_app_updateOsc
+                0x0000064c       0x76 cqm6xx_app.o
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+                0x000006c2       0x5a cqm6xx_app.o
+                0x000006c2                cqm6xx_app_statemachine
+ .text.programPLL_Parameters
+                0x0000071c       0x28 cqm6xx_app.o
+                0x0000071c                programPLL_Parameters
+ .text.uart_rx_event
+                0x00000744        0xe cqm6xx_app.o
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+                0x00000752       0x2c cqm6xx_app.o
+                0x00000752                cqm6xx_app_init
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-                0x00000160       0x10 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls\libattiny402.a(eerd_byte.o)
-                0x00000160                eeprom_read_byte
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+                0x00000e74                memcpy
+ .text.avr-libc
+                0x00000e86       0x10 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls\libattiny402.a(eerd_byte.o)
+                0x00000e86                eeprom_read_byte
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+                0x00000e96       0x28 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls\libattiny402.a(eewr_byte.o)
+                0x00000e96                eeprom_write_byte
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  *(.fini9)
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-                0x00000198                _exit
-                0x00000198                exit
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+                0x00000ebe                _exit
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+ .fini0         0x00000ebe        0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/avrxmega3/short-calls\libgcc.a(_exit.o)
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-                0x0000019c                _etext = .
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-.rodata
+.rodata         0x00008ec2        0x5 load address 0x00000ec2
  *(.rodata)
  *(.rodata*)
+ .rodata.startCode
+                0x00008ec2        0x5 cm_msg/cm_msg.o
  *(.gnu.linkonce.r*)
 
-.data           0x00803f00       0x1a load address 0x0000019c
+.data           0x00803f00        0x8 load address 0x00000ec7
                 0x00803f00                PROVIDE (__data_start, .)
  *(.data)
+ .data          0x00803f00        0x6 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/../../../../avr/lib/avrxmega3/short-calls\libc.a(malloc.o)
+                0x00803f00                __malloc_heap_end
+                0x00803f02                __malloc_heap_start
+                0x00803f04                __malloc_margin
  *(.data*)
- .data.data_set
-                0x00803f00       0x19 main.o
-                0x00803f00                data_set
+ .data.msg_ptr  0x00803f06        0x2 cqm6xx_app.o
+                0x00803f06                msg_ptr
  *(.gnu.linkonce.d*)
-                0x00803f1a                . = ALIGN (0x2)
- *fill*         0x00803f19        0x1 
-                0x00803f1a                _edata = .
-                0x00803f1a                PROVIDE (__data_end, .)
+                0x00803f08                . = ALIGN (0x2)
+                0x00803f08                _edata = .
+                0x00803f08                PROVIDE (__data_end, .)
 
-.bss            0x00803f1a       0x1c
-                0x00803f1a                PROVIDE (__bss_start, .)
+.bss            0x00803f08       0x63
+                0x00803f08                PROVIDE (__bss_start, .)
  *(.bss)
  *(.bss*)
  .bss.uart_rx_evt_fpt
-                0x00803f1a        0x2 avr_uart_driver/avr_uart.o
-                0x00803f1a                uart_rx_evt_fpt
- .bss.counter.3520
-                0x00803f1c        0x1 main.o
- .bss.data      0x00803f1d       0x19 main.o
-                0x00803f1d                data
+                0x00803f08        0x2 avr_uart_driver/avr_uart.o
+                0x00803f08                uart_rx_evt_fpt
+ .bss.msg.1844  0x00803f0a       0x37 cm_msg/cm_msg.o
+ .bss.data_bytes_idx.1845
+                0x00803f41        0x1 cm_msg/cm_msg.o
+ .bss.state.1843
+                0x00803f42        0x1 cm_msg/cm_msg.o
+ .bss.state.1832
+                0x00803f43        0x1 cm_msg/cm_msg.o
+ .bss.s_msg_cmplete_evt_inst
+                0x00803f44        0x2 cm_msg/cm_msg.o
+                0x00803f44                s_msg_cmplete_evt_inst
+ .bss.s_msg_cmplete_evt_fpt
+                0x00803f46        0x2 cm_msg/cm_msg.o
+                0x00803f46                s_msg_cmplete_evt_fpt
  *(COMMON)
-                0x00803f36                PROVIDE (__bss_end, .)
-                0x0000019c                __data_load_start = LOADADDR (.data)
-                0x000001b6                __data_load_end = (__data_load_start + SIZEOF (.data))
+ COMMON         0x00803f48       0x19 cqm6xx_app.o
+                0x00803f48                temp_msg
+ COMMON         0x00803f61        0x6 main.o
+                0x00803f61                storno_xtal_app
+ COMMON         0x00803f67        0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/../../../../avr/lib/avrxmega3/short-calls\libc.a(malloc.o)
+                0x00803f67                __brkval
+                0x00803f69                __flp
+                0x00803f6b                PROVIDE (__bss_end, .)
+                0x00000ec7                __data_load_start = LOADADDR (.data)
+                0x00000ecf                __data_load_end = (__data_load_start + SIZEOF (.data))
 
-.noinit         0x00803f36        0x0
+.noinit         0x00803f6b        0x0
                 [!provide]                PROVIDE (__noinit_start, .)
  *(.noinit*)
                 [!provide]                PROVIDE (__noinit_end, .)
-                0x00803f36                _end = .
-                0x00803f36                PROVIDE (__heap_start, .)
+                0x00803f6b                _end = .
+                0x00803f6b                PROVIDE (__heap_start, .)
 
 .eeprom         0x00810000        0x0
  *(.eeprom*)
@@ -757,8 +744,14 @@ END GROUP
  *(.comment)
  .comment       0x00000000       0x30 avr_eeprom_driver/avr_eeprom_driver.o
                                  0x31 (size before relaxing)
+ .comment       0x00000030       0x31 avr_gpio_driver/avr_gpio.o
+ .comment       0x00000030       0x31 avr_i2c_driver/avr_i2c.o
  .comment       0x00000030       0x31 avr_uart_driver/avr_uart.o
+ .comment       0x00000030       0x31 cm_msg/cm_msg.o
+ .comment       0x00000030       0x31 cqm6xx_app.o
  .comment       0x00000030       0x31 main.o
+ .comment       0x00000030       0x31 si5351_driver/si5351_driver.o
+ .comment       0x00000030       0x31 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/../../../../avr/lib/avrxmega3/short-calls\libc.a(malloc.o)
 
 .note.gnu.avr.deviceinfo
                 0x00000000       0x3c
@@ -780,70 +773,115 @@ END GROUP
 .debug_sfnames
  *(.debug_sfnames)
 
-.debug_aranges  0x00000000       0xc8
+.debug_aranges  0x00000000      0x260
  *(.debug_aranges)
  .debug_aranges
                 0x00000000       0x28 avr_eeprom_driver/avr_eeprom_driver.o
  .debug_aranges
-                0x00000028       0x40 avr_uart_driver/avr_uart.o
+                0x00000028       0x30 avr_gpio_driver/avr_gpio.o
  .debug_aranges
-                0x00000068       0x20 main.o
+                0x00000058       0x68 avr_i2c_driver/avr_i2c.o
  .debug_aranges
-                0x00000088       0x20 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls\libattiny402.a(eerd_byte.o)
+                0x000000c0       0x40 avr_uart_driver/avr_uart.o
  .debug_aranges
-                0x000000a8       0x20 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls\libattiny402.a(eewr_byte.o)
+                0x00000100       0x30 cm_msg/cm_msg.o
+ .debug_aranges
+                0x00000130       0x58 cqm6xx_app.o
+ .debug_aranges
+                0x00000188       0x20 main.o
+ .debug_aranges
+                0x000001a8       0x78 si5351_driver/si5351_driver.o
+ .debug_aranges
+                0x00000220       0x20 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls\libattiny402.a(eerd_byte.o)
+ .debug_aranges
+                0x00000240       0x20 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls\libattiny402.a(eewr_byte.o)
 
 .debug_pubnames
  *(.debug_pubnames)
 
-.debug_info     0x00000000     0x1e3d
+.debug_info     0x00000000     0x539c
  *(.debug_info .gnu.linkonce.wi.*)
  .debug_info    0x00000000     0x11d6 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls/crtattiny402.o
- .debug_info    0x000011d6      0x16d avr_eeprom_driver/avr_eeprom_driver.o
- .debug_info    0x00001343      0x4fc avr_uart_driver/avr_uart.o
- .debug_info    0x0000183f      0x4a4 main.o
- .debug_info    0x00001ce3       0xad C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls\libattiny402.a(eerd_byte.o)
- .debug_info    0x00001d90       0xad C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls\libattiny402.a(eewr_byte.o)
+ .debug_info    0x000011d6      0x16b avr_eeprom_driver/avr_eeprom_driver.o
+ .debug_info    0x00001341      0x320 avr_gpio_driver/avr_gpio.o
+ .debug_info    0x00001661      0x6da avr_i2c_driver/avr_i2c.o
+ .debug_info    0x00001d3b      0x4fc avr_uart_driver/avr_uart.o
+ .debug_info    0x00002237      0x2b4 cm_msg/cm_msg.o
+ .debug_info    0x000024eb      0x989 cqm6xx_app.o
+ .debug_info    0x00002e74      0xd18 main.o
+ .debug_info    0x00003b8c     0x16b6 si5351_driver/si5351_driver.o
+ .debug_info    0x00005242       0xad C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls\libattiny402.a(eerd_byte.o)
+ .debug_info    0x000052ef       0xad C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls\libattiny402.a(eewr_byte.o)
 
-.debug_abbrev   0x00000000     0x1565
+.debug_abbrev   0x00000000     0x1d9f
  *(.debug_abbrev)
  .debug_abbrev  0x00000000     0x10de C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls/crtattiny402.o
- .debug_abbrev  0x000010de       0xac avr_eeprom_driver/avr_eeprom_driver.o
- .debug_abbrev  0x0000118a      0x1e0 avr_uart_driver/avr_uart.o
- .debug_abbrev  0x0000136a      0x1d3 main.o
- .debug_abbrev  0x0000153d       0x14 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls\libattiny402.a(eerd_byte.o)
- .debug_abbrev  0x00001551       0x14 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls\libattiny402.a(eewr_byte.o)
+ .debug_abbrev  0x000010de       0xa0 avr_eeprom_driver/avr_eeprom_driver.o
+ .debug_abbrev  0x0000117e      0x107 avr_gpio_driver/avr_gpio.o
+ .debug_abbrev  0x00001285      0x1bb avr_i2c_driver/avr_i2c.o
+ .debug_abbrev  0x00001440      0x1e0 avr_uart_driver/avr_uart.o
+ .debug_abbrev  0x00001620      0x14b cm_msg/cm_msg.o
+ .debug_abbrev  0x0000176b      0x1e1 cqm6xx_app.o
+ .debug_abbrev  0x0000194c      0x1ec main.o
+ .debug_abbrev  0x00001b38      0x23f si5351_driver/si5351_driver.o
+ .debug_abbrev  0x00001d77       0x14 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls\libattiny402.a(eerd_byte.o)
+ .debug_abbrev  0x00001d8b       0x14 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls\libattiny402.a(eewr_byte.o)
 
-.debug_line     0x00000000      0x7d0
+.debug_line     0x00000000     0x18a4
  *(.debug_line .debug_line.* .debug_line_end)
  .debug_line    0x00000000      0x136 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls/crtattiny402.o
- .debug_line    0x00000136      0x166 avr_eeprom_driver/avr_eeprom_driver.o
- .debug_line    0x0000029c      0x21b avr_uart_driver/avr_uart.o
- .debug_line    0x000004b7      0x1d9 main.o
- .debug_line    0x00000690       0x7c C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls\libattiny402.a(eerd_byte.o)
- .debug_line    0x0000070c       0xc4 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls\libattiny402.a(eewr_byte.o)
+ .debug_line    0x00000136      0x186 avr_eeprom_driver/avr_eeprom_driver.o
+ .debug_line    0x000002bc      0x196 avr_gpio_driver/avr_gpio.o
+ .debug_line    0x00000452      0x3ff avr_i2c_driver/avr_i2c.o
+ .debug_line    0x00000851      0x21b avr_uart_driver/avr_uart.o
+ .debug_line    0x00000a6c      0x21a cm_msg/cm_msg.o
+ .debug_line    0x00000c86      0x3f6 cqm6xx_app.o
+ .debug_line    0x0000107c      0x18f main.o
+ .debug_line    0x0000120b      0x559 si5351_driver/si5351_driver.o
+ .debug_line    0x00001764       0x7c C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls\libattiny402.a(eerd_byte.o)
+ .debug_line    0x000017e0       0xc4 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls\libattiny402.a(eewr_byte.o)
 
-.debug_frame    0x00000000      0x140
+.debug_frame    0x00000000      0x694
  *(.debug_frame)
- .debug_frame   0x00000000       0x60 avr_eeprom_driver/avr_eeprom_driver.o
- .debug_frame   0x00000060       0xbc avr_uart_driver/avr_uart.o
- .debug_frame   0x0000011c       0x24 main.o
+ .debug_frame   0x00000000       0x7c avr_eeprom_driver/avr_eeprom_driver.o
+ .debug_frame   0x0000007c       0x44 avr_gpio_driver/avr_gpio.o
+ .debug_frame   0x000000c0      0x118 avr_i2c_driver/avr_i2c.o
+ .debug_frame   0x000001d8       0xbc avr_uart_driver/avr_uart.o
+ .debug_frame   0x00000294       0x44 cm_msg/cm_msg.o
+ .debug_frame   0x000002d8       0xfc cqm6xx_app.o
+ .debug_frame   0x000003d4       0x34 main.o
+ .debug_frame   0x00000408      0x28c si5351_driver/si5351_driver.o
 
-.debug_str      0x00000000      0xe53
+.debug_str      0x00000000     0x227c
  *(.debug_str)
  .debug_str     0x00000000      0x7a9 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.10.348/gcc/dev/attiny402/avrxmega3/short-calls/crtattiny402.o
- .debug_str     0x000007a9      0x1e2 avr_eeprom_driver/avr_eeprom_driver.o
-                                0x21b (size before relaxing)
- .debug_str     0x0000098b      0x353 avr_uart_driver/avr_uart.o
-                                0x4f4 (size before relaxing)
- .debug_str     0x00000cde      0x175 main.o
-                                0x3e5 (size before relaxing)
+ .debug_str     0x000007a9      0x1d9 avr_eeprom_driver/avr_eeprom_driver.o
+                                0x21f (size before relaxing)
+ .debug_str     0x00000982      0x16e avr_gpio_driver/avr_gpio.o
+                                0x319 (size before relaxing)
+ .debug_str     0x00000af0      0x2ab avr_i2c_driver/avr_i2c.o
+                                0x506 (size before relaxing)
+ .debug_str     0x00000d9b      0x283 avr_uart_driver/avr_uart.o
+                                0x4f8 (size before relaxing)
+ .debug_str     0x0000101e      0x23a cm_msg/cm_msg.o
+                                0x3fe (size before relaxing)
+ .debug_str     0x00001258      0x3c1 cqm6xx_app.o
+                                0x624 (size before relaxing)
+ .debug_str     0x00001619      0x908 main.o
+                                0xc65 (size before relaxing)
+ .debug_str     0x00001f21      0x35b si5351_driver/si5351_driver.o
+                                0xfbf (size before relaxing)
 
-.debug_loc      0x00000000      0x349
+.debug_loc      0x00000000     0x23ef
  *(.debug_loc)
- .debug_loc     0x00000000      0x1c6 avr_eeprom_driver/avr_eeprom_driver.o
- .debug_loc     0x000001c6      0x13b avr_uart_driver/avr_uart.o
- .debug_loc     0x00000301       0x48 main.o
+ .debug_loc     0x00000000      0x24e avr_eeprom_driver/avr_eeprom_driver.o
+ .debug_loc     0x0000024e       0xae avr_gpio_driver/avr_gpio.o
+ .debug_loc     0x000002fc      0x73d avr_i2c_driver/avr_i2c.o
+ .debug_loc     0x00000a39      0x13b avr_uart_driver/avr_uart.o
+ .debug_loc     0x00000b74      0x179 cm_msg/cm_msg.o
+ .debug_loc     0x00000ced      0x5f7 cqm6xx_app.o
+ .debug_loc     0x000012e4       0x48 main.o
+ .debug_loc     0x0000132c     0x10c3 si5351_driver/si5351_driver.o
 
 .debug_macinfo
  *(.debug_macinfo)
@@ -863,11 +901,16 @@ END GROUP
 .debug_pubtypes
  *(.debug_pubtypes)
 
-.debug_ranges   0x00000000       0x58
+.debug_ranges   0x00000000      0x1a0
  *(.debug_ranges)
  .debug_ranges  0x00000000       0x18 avr_eeprom_driver/avr_eeprom_driver.o
- .debug_ranges  0x00000018       0x30 avr_uart_driver/avr_uart.o
- .debug_ranges  0x00000048       0x10 main.o
+ .debug_ranges  0x00000018       0x20 avr_gpio_driver/avr_gpio.o
+ .debug_ranges  0x00000038       0x58 avr_i2c_driver/avr_i2c.o
+ .debug_ranges  0x00000090       0x30 avr_uart_driver/avr_uart.o
+ .debug_ranges  0x000000c0       0x20 cm_msg/cm_msg.o
+ .debug_ranges  0x000000e0       0x48 cqm6xx_app.o
+ .debug_ranges  0x00000128       0x10 main.o
+ .debug_ranges  0x00000138       0x68 si5351_driver/si5351_driver.o
 
 .debug_macro
  *(.debug_macro)
diff --git a/storno_cqp6xx_digital_xtal/Debug/storno_cqp6xx_digital_xtal.srec b/storno_cqp6xx_digital_xtal/Debug/storno_cqp6xx_digital_xtal.srec
index 09ef998..0b57597 100644
--- a/storno_cqp6xx_digital_xtal/Debug/storno_cqp6xx_digital_xtal.srec
+++ b/storno_cqp6xx_digital_xtal/Debug/storno_cqp6xx_digital_xtal.srec
@@ -1,30 +1,241 @@
 S022000073746F726E6F5F6371703678785F6469676974616C5F7874616C2E737265633F
 S113000019C033C032C031C030C02FC02EC02DC083
 S11300102CC02BC02AC029C028C027C026C025C098
-S113002024C023C022C021C020C01FC042C01DC0A4
+S113002024C023C022C021C020C01FC082C11DC063
 S11300301CC01BC011241FBECFEFCDBFDFE3DEBF4A
-S11300401FE3A0E0BFE3ECE9F1E002C005900D92EC
-S1130050AA31B107D9F72FE3AAE1BFE301C01D928A
-S1130060A633B207E1F750D097C0CACFEF92FF9200
+S11300401FE3A0E0BFE3E7ECFEE002C005900D92E1
+S1130050A830B107D9F72FE3A8E0BFE301C01D9290
+S1130060AB36B207E1F78BD32AC7CACFEF92FF9220
 S11300700F931F93CF93DF937C018B01D42FC0E0A8
-S113008007C0F801EC0FF11D6081C70171D0CF5F8B
-S1130090CD17B8F3DF91CF911F910F91FF90EF909F
-S11300A00895CF93DF93EB015BD08883DF91CF91E9
-S11300B008951F920F920FB60F9211242F933F931E
-S11300C04F935F936F937F938F939F93AF93BF935C
-S11300D0EF93FF93E0911A3FF0911B3F309719F093
-S11300E0809100080995FF91EF91BF91AF919F9185
-S11300F08F917F916F915F914F913F912F910F90CD
-S11301000FBE0F901F90189541E06DE17FE380E0F2
-S113011090E0C7DF2AE684E091E0215080409040DF
-S1130120E1F700C041E060E07FE380E090E09EDF23
-S1130130809108048D3059F480911C3F8F5F809327
-S11301401C3F80911C3F823310F010921C3F2AE622
-S113015084E091E0215080409040E1F700C0E8CF76
-S113016003D0808199270895FC01E050FC4E089546
-S1130170262FAF93BF93E0E0F0E1328131FDFDCF54
-S1130180DC01A050BC4E2C932DE924BF23E0208336
-S10F01900196BF91AF910895F894FFCF41
-S113019C55000000000000000000000000000000FA
-S10D01AC0000000000000000000045
+S11300800AC08C2F90E0F801E80FF91F60818E0DF3
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+S11301100895E0E1F8E084818860848381E0858348
+S113012008958093170880911508807CE1F39091DD
+S11301301508892F807194FF04C083E0809314080C
+S113014081E00895CF92DF92EF92FF92CF93DF93F5
+S1130150EB0169017A01232B242B252B81F1E1DFAB
+S1130160811130C09E012F5F3F4F88818093180812
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 S9030000FC
diff --git a/storno_cqp6xx_digital_xtal/avr_eeprom_driver b/storno_cqp6xx_digital_xtal/avr_eeprom_driver
index 31508be..5786c77 160000
--- a/storno_cqp6xx_digital_xtal/avr_eeprom_driver
+++ b/storno_cqp6xx_digital_xtal/avr_eeprom_driver
@@ -1 +1 @@
-Subproject commit 31508bec9dd34319737e697f753fc4a87c6823ab
+Subproject commit 5786c777ac4afc7fbbdb18f5a1ece4d06b79ac87
diff --git a/storno_cqp6xx_digital_xtal/cqm6xx_app.c b/storno_cqp6xx_digital_xtal/cqm6xx_app.c
index 9381d91..304db8a 100644
--- a/storno_cqp6xx_digital_xtal/cqm6xx_app.c
+++ b/storno_cqp6xx_digital_xtal/cqm6xx_app.c
@@ -16,6 +16,9 @@
 #define PLLA_SETTINGS_EEPROM_ADDR 0x00 // addr 0
 #define PLLB_SETTINGS_EEPROM_ADDR 0x20 // addr 32 (64 bytes total memory)
 
+	storno_pll_param_msg temp_msg;
+	uint8_t *msg_ptr = (void*)&temp_msg;
+
 static uint8_t isStructValid(storno_xtal_app_t *inst){
 	
 		if(inst->si5351_dev == NULL) return 1;
@@ -71,25 +74,23 @@ static void cqm_setPLLParam(storno_xtal_app_t *inst, si5351_PLLs pll_num, si5351
 
 static void cqm6xx_app_loadPLLParam(storno_xtal_app_t *inst){
 	
-	/*cm_setInputSource(inst->si5351_dev, SI5351_CLK_SOURCE_XTAL);
+	cm_setInputSource(inst->si5351_dev, SI5351_CLK_SOURCE_XTAL);
 	_delay_ms(1);
-	
-	storno_pll_param_msg temp_msg;
-	uint8_t *msg_ptr = (void*)&temp_msg;
-	
-	cm_EEPROM_read(PLLA_SETTINGS_EEPROM_ADDR,msg_ptr,sizeof(storno_pll_param_msg));
+
 	inst->pll_param_ptr = &temp_msg;
+	cm_EEPROM_read(PLLA_SETTINGS_EEPROM_ADDR,msg_ptr,sizeof(storno_pll_param_msg));
+	
 	cqm_setPLLParam(inst, SI5351_PLL_A, SI5351_OUTPUT_0);
 	cm_setCLKControl(inst->si5351_dev,SI5351_OUTPUT_0,SI5351_CLK_POWER_UP);
 	_delay_ms(1);
 	
 	
-	cm_EEPROM_read(PLLB_SETTINGS_EEPROM_ADDR,msg_ptr,sizeof(storno_pll_param_msg));
-	inst->pll_param_ptr = &temp_msg;
-	cqm_setPLLParam(inst, SI5351_PLL_B, SI5351_OUTPUT_1);
-	cm_setCLKControl(inst->si5351_dev,SI5351_OUTPUT_1,SI5351_CLK_POWER_UP);
+	//cm_EEPROM_read(PLLB_SETTINGS_EEPROM_ADDR,msg_ptr,sizeof(storno_pll_param_msg));
+	//inst->pll_param_ptr = &temp_msg;
+	//cqm_setPLLParam(inst, SI5351_PLL_B, SI5351_OUTPUT_1);
+	//cm_setCLKControl(inst->si5351_dev,SI5351_OUTPUT_1,SI5351_CLK_POWER_UP);
 	
-	inst->pll_param_ptr = NULL;*/
+	//inst->pll_param_ptr = NULL;
 	
 	
 }
@@ -155,11 +156,11 @@ void programPLL_Parameters(storno_xtal_app_t *inst){
 	switch(inst->pll_param_ptr->PLL_Ident){
 		
 		case MSG_PLLA_PARAM:
-			//cm_EEPROM_write(PLLA_SETTINGS_EEPROM_ADDR,(uint8_t*)(inst->pll_param_ptr), sizeof(storno_pll_param_msg));	
+			cm_EEPROM_write(PLLA_SETTINGS_EEPROM_ADDR,(uint8_t*)(inst->pll_param_ptr), sizeof(storno_pll_param_msg));	
 		break;
 		
 		case MSG_PLLB_PARAM:
-			//cm_EEPROM_write(PLLB_SETTINGS_EEPROM_ADDR,(uint8_t*)(inst->pll_param_ptr), sizeof(storno_pll_param_msg));
+			cm_EEPROM_write(PLLB_SETTINGS_EEPROM_ADDR,(uint8_t*)(inst->pll_param_ptr), sizeof(storno_pll_param_msg));
 		break;
 		
 	}
@@ -167,7 +168,7 @@ void programPLL_Parameters(storno_xtal_app_t *inst){
 	// Send status back maybe.. 
 	
 	//Force state machine to load new settings from eeprom:
-	inst->state_next = STORNO_APP_PROGRAM_OSC;
+	//inst->state_next = STORNO_APP_PROGRAM_OSC;
 	
 }
 
@@ -175,7 +176,7 @@ int uart_rx_event(storno_xtal_app_t *inst, void *rxData){
 	
 	inst->pll_param_ptr = rxData;
 	
-	//programPLL_Parameters(inst);
+	programPLL_Parameters(inst);
 	
 	return 0;
 	
diff --git a/storno_cqp6xx_digital_xtal/cqm6xx_app.h b/storno_cqp6xx_digital_xtal/cqm6xx_app.h
index 128eddb..6d057bd 100644
--- a/storno_cqp6xx_digital_xtal/cqm6xx_app.h
+++ b/storno_cqp6xx_digital_xtal/cqm6xx_app.h
@@ -51,7 +51,7 @@ typedef struct {
 	
 	void *si5351_dev;
 	storno_pll_param_msg *pll_param_ptr;
-	
+	storno_pll_param_msg pll_param_data;
 	
 	
 	
diff --git a/storno_cqp6xx_digital_xtal/main.c b/storno_cqp6xx_digital_xtal/main.c
index 36ec947..b3ba210 100644
--- a/storno_cqp6xx_digital_xtal/main.c
+++ b/storno_cqp6xx_digital_xtal/main.c
@@ -15,33 +15,26 @@
 
 storno_xtal_app_t storno_xtal_app;
 
-	uint8_t data_set[25] = {0x55};
+	uint8_t data_set[25] = {0x55,56};
 	//cm_EEPROM_write(0x00,data_set,1);
 	uint8_t data[25] = {0};
 		
 int main(void)
 {
-	
-
-	cm_EEPROM_read(0x00,data,1);
-	
-	_delay_ms(100);
-	
-	cm_EEPROM_write(0x00,data_set,1);
     /* Replace with your application code */
 
 		// Init Periphials
-		//cm_i2c_init(NULL);
+		cm_i2c_init(NULL);
 		
 		// Add devices
-		//cm_i2c_device_t si5351_i2c;
-		//cm_i2c_addDev(&si5351_i2c,NULL,0x60);
+		cm_i2c_device_t si5351_i2c;
+		cm_i2c_addDev(&si5351_i2c,NULL,0x60);
 		
 		// Init Devices:
-		//si5351_driver si5351_dev;
-		//cm_si5351_init(&si5351_dev,&si5351_i2c,(setGet_I2C_Event_fpt)cm_i2c_transfer);
+		si5351_driver si5351_dev;
+		cm_si5351_init(&si5351_dev,&si5351_i2c,(setGet_I2C_Event_fpt)cm_i2c_transfer);
 		
-		//cqm6xx_app_init(&storno_xtal_app, &si5351_dev);
+		cqm6xx_app_init(&storno_xtal_app, &si5351_dev);
 		
 		
 		
@@ -49,22 +42,7 @@ int main(void)
     while (1) 
     {
 
-		//cqm6xx_app_statemachine(&storno_xtal_app);
-	if(PORTA.IN == 0x0d){
-	
-		static volatile uint8_t counter = 0;
-		
-		counter++;
-		
-		if (counter >= 50)
-		{
-			counter = 0;
-		}
-	
-	}
-	
-	
-	
+		cqm6xx_app_statemachine(&storno_xtal_app);
 		_delay_ms(100);
     }
 }